matched filter in vhdl
Abstract: digital FIR Filter VHDL code xilinx code fir filter in vhdl vhdl code 16 bit processor XAPP212 transposed fir Filter VHDL code vhdl code for 8-bit serial adder matched filter hdl codes pulse shaping FILTER implementation xilinx vhdl code PN code
Contextual Info: Application Note: Virtex Series and Virtex-II Series CDMA Matched Filter Implementation in Virtex Devices R XAPP212 v1.1 January 10, 2001 Author: Ken Chapman, Paul Hardy, Andy Miller, and Maria George Summary Code Division Multiple Access (CDMA) is a rapidly expanding data transmission technique in
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xapp212com/pub/applications/xapp/xapp212matched filter in vhdldigital fir filter vhdl code+7xilinx code fir filter in vhdlvhdl code 16 bit processortransposed fir filter vhdl codevhdl code for 8-bit serial addermatched filter hdl codespulse shaping filter implementation xilinxvhdl code pn code
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dct verilog code
Abstract: VHDL code DCT vhdl code for matrix multiplication XAPP610 verilog code for matrix multiplication dct algorithm verilog code jpeg encoder vhdl code verilog for 8 point dct in xilinx matrix element addition Vhdl code XAPP208
Contextual Info: Application Note: Virtex-II Series R Video Compression Using DCT Author: Latha Pillai XAPP610 v1.2 April 24, 2002 Summary This application note describes a two-dimensional Discrete Cosine Transform (2D DCT) function implemented on a Xilinx FPGA. The reference design file provides behavioral code for
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xapp610dct verilog codevhdl code dctvhdl code for matrix multiplication+6verilog code for matrix multiplicationdct algorithm verilog codejpeg encoder vhdl codeverilog for 8 point dct in xilinxmatrix element addition vhdl codexapp208
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matched filter in vhdl
Abstract: digital FIR Filter VHDL code matched filter hdl codes XAPP212 vhdl code for 8-bit serial adder pulse shaping FILTER implementation xilinx 8 bit fir filter vhdl code vhdl code for cdma vhdl code for multiplexer 64 to 1 using 8 to 1 SRL16
Contextual Info: Application Note: Virtex Series R XAPP212 v1.0 March 31, 2000 CDMA Matched Filter Implementation in Virtex Devices Author: Ken Chapman, Paul Hardy, Andy Miller, and Maria George Summary Code Division Multiple Access (CDMA) is a rapidly expanding data transmission technique in
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xapp212com/pub/applications/xapp/xapp212matched filter in vhdldigital fir filter vhdl code+7matched filter hdl codesvhdl code for 8-bit serial adderpulse shaping filter implementation xilinx8 bit fir filter vhdl codevhdl code for cdmavhdl code for multiplexer 64 to 1 using 8 to 1srl16
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4 bit parallel adder
Abstract: 32 bit adder vhdl code 16 word 8 bit ram using vhdl vhdl code for 8 bit ram correlator 2128 RAM binary pattern signal generator vhdl code for 4 bit ram 16x3 serial correlator
Contextual Info: One Dimensional RAM-Based Correlator February 8, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: dsp@xilinx.com URL: www.xilinx.com Features • • • • • • • • •
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xc4000e4 bit parallel adder32 bit adder vhdl code16 word 8 bit ram using vhdl+7vhdl code for 8 bit ramcorrelator2128 rambinary pattern signal generatorvhdl code for 4 bit ram16x3serial correlator
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verilog code for 16 bit carry select adder
Abstract: X8978 verilog code of 8 bit comparator 8 bit carry select adder verilog codes UNSIGNED SERIAL DIVIDER using verilog SR-4X verilog code for johnson counter asm chart ieee vhdl verilog code for half subtractor
Contextual Info: Xilinx Synthesis Technology XST User Guide Introduction HDL Coding Techniques FPGA Optimization CPLD Optimization Design Constraints VHDL Language Support Verilog Language Support Command Line Mode XST Naming Conventions XST User Guide — 3.1i Printed in U.S.A.
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xc2064xc3090xc4005xc5210+11xc-ds501verilog code for 16 bit carry select adderx8978verilog code of 8 bit comparator8 bit carry select adder verilog codesunsigned serial divider using verilogsr-4xverilog code for johnson counterasm chartieee vhdlverilog code for half subtractor
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32 bit adder vhdl code
Abstract: 4 bit parallel adder serial correlator vhdl code for parallel to serial shift register vhdl code for correlator
Contextual Info: One Dimensional ROM-Based Correlator July 31, 1997 Product Specification R • • • DSP CORE Generator Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: dsp@xilinx.com URL: www.xilinx.com Features • •
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xc4000e-132 bit adder vhdl code4 bit parallel adderserial correlator+2vhdl code for parallel to serial shift registervhdl code for correlator
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accumulator xilinx v7.0
Abstract: false DS213 low power and area efficient carry select adder
Contextual Info: Accumulator v7.0 DS213 April 28, 2005 Product Specification Features • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Generates Add, Subtract, and Add/Subtract-based
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ds213accumulator xilinx v7.0falselow power and area efficient carry select adder |
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80C31 instruction set
Abstract: xc2s200 pq208 xilinx code for 8-bit serial adder dvb-RCS transmitter XC2S50 driver PIC Microcontroller GSM Modem POS-PHY ATM format dvb-RCS modulator uart 16450 128-bit key generation matlab code for image enc
Contextual Info: XILINX IP SELECTION GUIDE Implementation Example Function Communication & Networking BUFE-based Multiplexer Slice 3G FEC Package 3GPP Compliant Turbo Convolutional Decoder 3GPP Compliant Turbo Convolutional Encoder 3GPP Turbo Decoder 8b/10b Decoder 8b/10b Encoder
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8b/10bdo-di-adpcm32do-di-adpcm64cc-201+15cc-200crc10cc-130crc32cc-13180c31 instruction setxc2s200 pq208xilinx code for 8-bit serial adderdvb-rcs transmitterxc2s50 driverpic microcontroller gsm modempos-phy atm formatdvb-rcs modulatoruart 16450128-bit key generation matlab code for image enc
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vhdl code for carry select adder using ROM
Abstract: 32 bit carry select adder in vhdl serial correlator vhdl code for carry select adder correlator XC4000E X8827 vhdl code for correlator
Contextual Info: One Dimensional Serial ROM-Based Correlator December 30, 1998 Product Specification R • Relational Placed Macro RPM mapping and placement technology Available in Xilinx Core Generator Tool Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778
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12-bitsx8829vhdl code for carry select adder using rom32 bit carry select adder in vhdl+6serial correlatorvhdl code for carry select addercorrelatorxc4000ex8827vhdl code for correlator
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verilog code for modified booth algorithm
Abstract: vhdl code for Booth multiplier vhdl code for pipelined matrix multiplication verilog code for matrix multiplication 8 bit booth multiplier vhdl code booth multiplier code in vhdl vhdl code for matrix multiplication vhdl code for 8bit booth multiplier matrix multiplier Vhdl code verilog code pipeline square root
Contextual Info: Application Note: Spartan-3 R Using Embedded Multipliers in Spartan-3 FPGAs XAPP467 v1.1 May 13, 2003 Summary Dedicated 18x18 multipliers speed up DSP logic in the Spartan -3 family. The multipliers are fast and efficient at implementing signed or unsigned multiplication of up to 18 bits. In addition
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xapp46718x18xc3s50verilog code for modified booth algorithm+9vhdl code for booth multipliervhdl code for pipelined matrix multiplicationverilog code for matrix multiplication8 bit booth multiplier vhdl codebooth multiplier code in vhdlvhdl code for matrix multiplicationvhdl code for 8bit booth multipliermatrix multiplier vhdl codeverilog code pipeline square root
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false
Abstract: DS214 low power and area efficient carry select adder adder xilinx
Contextual Info: Adder/Subtracter v7.0 DS214 April 28, 2005 Product Specification Features • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs • Generates Adder, Subtracter and Adder/Subtracter
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ds214falselow power and area efficient carry select adderadder xilinx |
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12-bit ADC interface vhdl code for FPGA
Abstract: 12-bit ADC interface vhdl complete code for FPGA verilog code for 8 bit shift register theory IPC-2141 VHDL code for high speed ADCs using SPI with FPGA ADC Verilog Implementation XAPP268 XAPP774 emif vhdl fpga XAPP623
Contextual Info: Application Note: Virtex-II, Virtex-II Pro, and Spartan-3 Families Connecting Xilinx FPGAs to Texas Instruments ADS527x Series ADCs R XAPP774 v1.2 February 23, 2006 Author: Marc Defossez Summary This application note describes how to connect a high-speed Texas Instruments (TI) ADS5273
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ads527xxapp774ads527312-bit+912-bit adc interface vhdl code for fpga12-bit adc interface vhdl complete code for fpgaverilog code for 8 bit shift register theoryipc-2141vhdl code for high speed adcs using spi with fpgaadc verilog implementationxapp268emif vhdl fpgaxapp623
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80C31 instruction set
Abstract: XC2S200 pq208 xilinx fifo generator 6.2 application of 8259 microcontroller design BCD adder pal dvb-RCS modem hitachi pbx AX1610 MC68000 opcodes adder xilinx
Contextual Info: Vendor Name IP Type Xilinx Xilinx Xilinx sysonchip Xilinx Xilinx Amphion Amphion Amphion Amphion Amphion Xilinx Xilinx NewLogic LogiCORE LogiCORE LogiCORE AllianceCORE LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiCORE
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8b/10bdo-di-adpcm32do-di-adpcm64cc-201+15cc-200crc10cc-130crc32cc-13180c31 instruction setxc2s200 pq208xilinx fifo generator 6.2application of 8259 microcontrollerdesign bcd adder paldvb-rcs modemhitachi pbxax1610mc68000 opcodesadder xilinx
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verilog code of 4 bit magnitude comparator
Abstract: verilog code of 8 bit comparator Verilog code for 2s complement of a number Verilog code subtractor 8 bit full adder VHDL verilog code for half subtractor vhdl code for 8-bit signed adder verilog code of 16 bit comparator XAPP215 multiplier accumulator MAC code VHDL
Contextual Info: Application Note: Virtex Series R XAPP215 v1.0 June 28, 2000 Design Tips for HDL Implementation of Arithmetic Functions Author: Steven Elzinga, Jeffrey Lin, and Vinita Singhal Summary This application note provides design advice for implementing arithmetic logic functions in two
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xapp215verilog code of 4 bit magnitude comparatorverilog code of 8 bit comparatorverilog code for 2s complement of a number+6verilog code subtractor8 bit full adder vhdlverilog code for half subtractorvhdl code for 8-bit signed adderverilog code of 16 bit comparatormultiplier accumulator mac code vhdl
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verilog code for distributed arithmetic
Abstract: verilog code image processing filtering 16 bit multiplier VERILOG circuit vhdl code for ROM multiplier XAPP283 verilog code for implementation of rom verilog code for 16 bit multiplier verilog code for Complement image xapp283.zip rgb yuv Verilog
Contextual Info: Application Note: Virtex-II Series R Color Space Converter Author: Latha Pillai XAPP283 v1.2 June 26, 2002 Summary This application note describes three ways to implement the Y’CrCb Color Space to R’G’B’ Color Space conversion necessary in many video designs. The tick marks on red, green, blue,
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xapp28310-bitverilog code for distributed arithmeticverilog code image processing filtering+716 bit multiplier verilog circuitvhdl code for rom multiplierverilog code for implementation of romverilog code for 16 bit multiplierverilog code for complement imagexapp283.ziprgb yuv verilog
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matlab codes for wcdma rake receiver
Abstract: 3G HSDPA circuits diagram HSDPA matlab wcdma simulink turbo encoder circuit, VHDL code mimo model simulink 3G HSDPA cell capacity planning hsdpa matlab codes 3g hsdpa signal antenna Diagram umts turbo encoder circuit
Contextual Info: Application Note: Virtex-4 and Spartan-3 Devices Benefits of FPGAs in Wireless Base Station Baseband Processing Applications R XAPP726 v1.0 July 25, 2005 Summary Author: Hong-Swee Lim With the deployment of the 3G-wireless infrastructure gaining momentum, equipment
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xapp726pp1064-1070matlab codes for wcdma rake receiver3g hsdpa circuits diagram+8hsdpa matlabwcdma simulinkturbo encoder circuit, vhdl codemimo model simulink3g hsdpa cell capacity planninghsdpa matlab codes3g hsdpa signal antenna diagramumts turbo encoder circuit
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16 bit multiplier VERILOG
Abstract: verilog code image processing filtering 64 bit multiplier VERILOG XAPP283 8 bit multiplier VERILOG color space look-up table mapping rgb yuv Verilog XC2V500 XC2V500-5 Xilinx XC2V500
Contextual Info: Application Note: Virtex-II Series R Color Space Converter Author: Latha Pillai XAPP283 v1.3 July 3, 2003 Summary This application note describes three ways to implement the Y'CrCb Color Space to R'G'B' Color Space conversion necessary in many video designs. The tick marks on red, green, blue,
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xapp28310-bit16 bit multiplier verilogverilog code image processing filtering+764 bit multiplier verilog8 bit multiplier verilogcolor space look-up table mappingrgb yuv verilogxc2v500xc2v500-5xilinx xc2v500
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16 bit multiplier VERILOG
Abstract: multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog vhdl code for accumulator addition accumulator MAC code verilog 16 bit multiplier VERILOG circuit multiplier accumulator unit with VHDL verilog code for 16 bit multiplier MULT18X18S XAPP636
Contextual Info: Application Note: Virtex-II Family R XAPP636 v1.4 June 24, 2004 Summary Optimal Pipelining of I/O Ports of the Virtex-II Multiplier Author: Markus Adhiwiyogo This application note and reference design describes a high-speed, optimized implementation of a Virtex -II pipelined multiplier primitive (MULT18X18 and MULT18X18S) implemented in
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xapp636mult18x18mult18x18s16 bit multiplier verilog+7multiplier accumulator mac code vhdlmultiplier accumulator mac code verilogvhdl code for accumulatoraddition accumulator mac code verilog16 bit multiplier verilog circuitmultiplier accumulator unit with vhdlverilog code for 16 bit multiplier
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vhdl code 16 bit LFSR
Abstract: vhdl code 8 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR vhdl code 16 bit LFSR with VHDL simulation output verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR verilog code 5 bit LFSR pseudo random generator
Contextual Info: Channel January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and
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i-10148vhdl code 16 bit lfsrvhdl code 8 bit lfsrvhdl code 4 bit lfsr+7vhdl code 10 bit lfsrvhdl code 16 bit lfsr with vhdl simulation outputverilog code 8 bit lfsrverilog code 16 bit lfsrverilog code 32 bit lfsrverilog code 5 bit lfsrpseudo random generator
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XC6200
Abstract: c code for interpolation and decimation filter vhdl code for interpolation CIC Filter vhdl code for cic Filter FPGA CIC Filter vhdl code for decimator CIC Filter CIC interpolation Filter XC6216 CIC Filter xilinx code fir filter in vhdl
Contextual Info: APPLICATION NOTE High Performance, Low Area, Interpolator Design for the XC6200 XAPP 081 May 7, 1997 Version 1.0 Application Note by Beth Cowie Summary An Interpolator FIR filter design for the XC6200 is discussed. Xilinx Family XC6200 Demonstrates The suitability of the XC6200 for CIC Filters and general DSP.
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xc6200c code for interpolation and decimation filtervhdl code for interpolation cic filtervhdl code for cic filter+6fpga cic filtervhdl code for decimator cic filtercic interpolation filterxc6216cic filterxilinx code fir filter in vhdl
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MZ80 sensor
Abstract: crt monitor circuit diagram intex 171 8086 microprocessor based project on weight AT89C51 opcode SL100 pin configuration interfacing Atmel 89C51 with ir sensors Block Diagram of 8279 micro processor generation of control signals in 89c51 micro keypad 4x6 matrix led interfacing with 89C51
Contextual Info: R 1. Introduction 2. LogiCORE Products 3. AllianceCORE Products 4. LogiBLOX 5. Reference Designs Section Titles R Table of Contents Introduction Introduction Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
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xc4000-seriesxc3000xc4000xc5000+13xapp028xapp028vxapp028omz80 sensorcrt monitor circuit diagram intex 1718086 microprocessor based project on weightat89c51 opcodesl100 pin configurationinterfacing atmel 89c51 with ir sensorsblock diagram of 8279 micro processorgeneration of control signals in 89c51 microkeypad 4x6 matrixled interfacing with 89c51
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traffic light c language
Abstract: behavioral code of carry save adder 32 bit carry select adder code 4 BIT ADDER ABEL updown counter XAPP075 XC7300 XC9500 design counter traffic light
Contextual Info: Using ABEL with Xilinx CPLDs XAPP075 January, 1997 Version 1.0 Application Note Summary This application note provides a basic overview of the ABEL language and gives examples showing how to use ABEL to fully utilize the specific features of Xilinx CPLDs.
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xapp075xc9500xc7300traffic light c language+5behavioral code of carry save adder32 bit carry select adder code4 bit adder abelupdown counterdesign counter traffic light
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verilog code pipeline ripple carry adder
Abstract: verilog code 8 bit LFSR application verilog code 8 bit LFSR verilog code for johnson counter 2 bit magnitude comparator using 2 xor gates LFSR COUNTER vhdl code up/down 8-bit LFSR synopsys Platform Architect DataSheet BUT30 XC3000A
Contextual Info: LogiBLOX Guide Introduction Getting Started Understanding Attributes Module Descriptions LogiBLOX Versus X-BLOX/ Memgen LogiBLOX Guide Printed in U.S.A. LogiBLOX Guide R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE,
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xc2064xc3090xc4005xc5210+11xc-ds501verilog code pipeline ripple carry adderverilog code 8 bit lfsr applicationverilog code 8 bit lfsrverilog code for johnson counter2 bit magnitude comparator using 2 xor gateslfsr countervhdl code up/down 8-bit lfsrsynopsys platform architect datasheetbut30xc3000a
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traffic light c language
Abstract: design counter traffic light 4 BIT ADDER ABEL XC7300 XC9500 carry select adder 16 bit using fast adders 32 bit carry select adder code behavioral code of carry save adder
Contextual Info: Using ABEL with Xilinx CPLDs XAPP 075 - January, 1997 Version 1.0 Application Note Summary This application note provides a basic overview of the ABEL language and gives examples showing how to use ABEL to fully utilize the specific features of Xilinx CPLDs.
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xc9500xc7300traffic light c languagedesign counter traffic light+44 bit adder abelcarry select adder 16 bit using fast adders32 bit carry select adder codebehavioral code of carry save adder
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