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Contextual Info: P R U tflO G O M V in te i l n t e l 486 TM DX CPU-CACHE CHIP SET 50 MHz Intel486 DX Microprocessor, 82495DX Cache Controller, and 82490DX Dual Ported Intelligent Cache SRAM • 50 MHz Intel486™ DX CPU — RISC Integer Core with Frequent Instructions Executing in One Clock

MSB2521

Abstract: 144-GPY2 sds rsl2 BUX 127 5-bf7 67-SD15 BC011 TGS 815 85A7 WD61C96A
Contextual Info: INTRODUCTION WD61C96A 1.0 INTRODUCTION 1.1 GENERAL DESCRIPTION 1.1.3 This document describes a single chip VLSI Peripheral Cache Manager, SCSI bus controller, and Disk Controller device, the WD61C96A, for target mode of operation. The WD61C96A is a highly integrated CMOS VLSI device which