1364 Search Results

20306

Abstract: TSOP31238SD1 03Technical
Contextual Info: SD1 Vishay Semiconductors IR Receiver Modules for Remote Control Systems FEATURES • Compliant to RoHS directive 2002/95/EC and in accordance to WEEE 2002/96/EC AVAILABLE FOR: • TSOP31. 1 • TSOP1. 2 13645 “H” “X” 3 “W” 20258 NAME LENS AXIS X

verilog code for vending machine

Abstract: verilog code for two 32 bit adder verilog code for vending machine using finite state machine vending machine verilog HDL file verilog code for digital clock verilog code finite state machine complete fsm of vending machine verilog code for 16 bit ram vhdl code for vending machine digital clock verilog code
Contextual Info: 3115/C CY3110/CY3115/CY3110J Warp2 Verilog Compiler for CPLDs Features — Ability to probe internal nodes — Display of inputs, outputs, and High Z signals in different colors • Verilog IEEE 1364 high-level language compiler — Facilitates device independent design

moa2

Abstract: 7816-6A1 HC 8332 SL2FCS5001 SL2FCS5101 i-code 2 tag chip SOT500AA1 ICODE SLI DSFI ICODE SLI-L
Contextual Info: SL2 ICS50/SL2 ICS51 I•CODE SLI-L/I•CODE SLI-L HC Rev. 3.0 — 14 March 2007 136430 Product data sheet PUBLIC 1. General description The I•CODE SLI-L/I•CODE SLI-L HC IC is a dedicated chip for smart label applications with the need for a leaner custom-specific command set, smaller memory and/or a

KK-1364-60

Abstract: on 707
Contextual Info: KK-1364-60 This EMI / RFI filter is intended to provide noise reduction for telecommunications DC power. The components used in the production are capable of passing the UL 707 Volt dielectric withstanding test for telecom equipment. The filter is non-polarized.

vhdl code for vending machine

Abstract: vhdl vending machine report vending machine schematic diagram FSM VHDL vending machine hdl vending machine vhdl code 7 segment display WARP drinks vending machine circuit vhdl code for soda vending machine block diagram vending machine
Contextual Info: CY3128 Warp Professional CPLD Software — Delta39K™ CPLDs Features — Quantum38K™ CPLDs • VHDL IEEE 1076 and 1164 and Verilog (IEEE 1364) high-level language compilers with the following features: — Designs are portable across multiple devices

20306

Abstract: Remote-control Receiver Module TSOP31238SE1 TSOP312 TSOP11238 TSOP311
Contextual Info: SE1 Vishay Semiconductors IR Receiver Modules for Remote Control Systems Features • Compliant with RoHS 2002/95/EC and WEEE 2002/96/EC e3 Available for: TSOP312. TSOP311. TSOP12. TSOP11. TSOP11238 1 2 13646 “H” 3 “X” • • • • • “W”

Contextual Info: RF1 Vishay Semiconductors IR Receiver Modules for Remote Control Systems FEATURES • Compliant to RoHS Directive 2002/95/EC and in accordance to WEEE 2002/96/EC AVAILABLE FOR: • TSOP31. 1 • TSOP1. 2 3 13640 “D” “H” “X” “W” 20249 NAME

12831

Contextual Info: SK1 Vishay Semiconductors IR Receiver Modules for Remote Control Systems AVAILABLE FOR: • TSOP31. • TSOP1. 1 2 13646 “H” “X” 3 “W” 20258 NAME LENS AXIS X SK1 17.8 VIEW TYPE HEIGHT (H) WIDTH (W) Cut 21.1 10 DEPTH (D) MECHANICAL DIMENSIONS in millimeters

c 828

Abstract: 1057 k 1006 L-1031 MO-211
Contextual Info: R REV PKG SYMM £ E V I S I O N S D E SC R IP T IO N A RELEASE B REM OVE TOP S I D E RENUMBER NOTES. TO DO CUME NT C O NT ROL COATING. IT S D IM & NOTE 1; E.C .N . DATE 1364 02/03/2004 Br/ A PP 'D MS/VP 1391 02/17/2004 M S/ HN DIMENSIONS ARE IN MILLIMETERS

104744

Contextual Info: PRAVIMS HADE IN THIRD AW3LE PROJECTION HIS DRAUIH3 13 UNPUBLISHED. I RELE ftEVtSIÛNS REL -3 AMD - A REV PER 0010-0960-94 REV PER EC 0010-1364-94 REV PER EC 0010-0631-95 REV PER EC 0010-0362-95 REV PER EC 0010-0035-96 REV PER 0010-0716-96 REV PER 0410-0190-96

HM66AQB18202

Abstract: HM66AQB18202BP-40 HM66AQB36102 HM66AQB36102BP-40 HM66AQB36102BP-50 HM66AQB36102BP-60 HM66AQB9402
Contextual Info: HM66AQB36102/HM66AQB18202 HM66AQB9402 TM 36-Mbit QDR II SRAM 2-word Burst REJ03C0049-0001Z Previous ADE-203-1364 (Z Rev. 0.0) Preliminary Rev.0.01 Mar.31.2004 Description The HM66AQB36102 is a 1,048,576-word by 36-bit, the HM66AQB18202 is a 2,097,152-word by 18-bit,

20312

Abstract: 81433 ir receiver transistor TSOP31238WI1
Contextual Info: WI1 Vishay Semiconductors IR Receiver Modules for Remote Control Systems FEATURES • Compliant with RoHS WEEE 2002/96/EC 2002/95/EC and e3 AVAILABLE FOR: • TSOP31. • TSOP1. 3 13643 “D” “H” “X” “W” 20248 NAME LENS AXIS X VIEW TYPE

Contextual Info: Part Details for P/N: 1364150-1 Products | Catalog | Brands | Industries | Commerce | Supplier | Contact Us | About | Home Home Part Number Search Document Search Sockets PGA Sockets AMP 1364150-1 Active Active Tyco Electronics P/N: 1364150-1 ELV Compliant ELV Compliant

Contextual Info: Part Details for P/N: 1364994-2 Products | Catalog | Brands | Industries | Commerce | Supplier | Contact Us | About | Home Home Part Number Search Document Search Sockets PGA Sockets AMP 1364994-2 Active Active Tyco Electronics P/N: 1364994-2 Not Reviewed for ELV/RoHS Compliance

Remote-control Receiver Module

Abstract: TSOP31238 TSOP31238RF1 "ir receiver"
Contextual Info: RF1 Vishay Semiconductors IR Receiver Modules for Remote Control Systems FEATURES • Compliant with RoHS WEEE 2002/96/EC 2002/95/EC and e3 AVAILABLE FOR: • TSOP31. 1 • TSOP1. 2 3 13640 “D” “X” “H” “W” 20249 NAME LENS AXIS X VIEW

vending machine using fsm

Abstract: vending machine source code easy examples of vhdl program SIGNAL PATH DESIGNER vhdl code 7 segment display vending machine verilog HDL file drink VENDING MACHINE circuit diagram
Contextual Info: 8 CY3128 Warp Professional CPLD Software — Delta39K™ CPLDs Features — Quantum38K™ CPLDs • VHDL IEEE 1076 and 1164 and Verilog (IEEE 1364) high-level language compilers with the following features: — Designs are portable across multiple devices

Contextual Info: Digitally Programmable data delay Delay Units SERIES: PDU-1364F d evices^ 6-Bit TTL Interfaced Features: • Input & output TTL buffered ■ 6-BIT TTL programmable delay line ■ Two (2) separate outputs; inverting & non-inverting ■ Completely Interfaced

dvi transmitter 1364

Abstract: Silicon Image 1364 DVI dual link receiver 1362clu DVI Link pin configuration Silicon image SiI 1364 1364CTU tmds specification SiI1362 SII1364CTU
Contextual Info: SiI 1364 and SiI 1362 PanelLink Transmitters The SiI 1364 and SiI 1362 are the world’s first fully compliant Serial Digital Video Output SDVO -based DVI transmitters that support the full operating range of Intel’s SDVO input port (1-2 GHz) and the full scalable DVI

Contextual Info: Part Details for P/N: 1364561-6 Products | Catalog | Brands | Industries | Commerce | Supplier | Contact Us | About | Home Home Part Number Search Document Search Cable Assemblies and Interface Devices Cable Assemblies AMP 1364561-6 Active Active Tyco Electronics P/N: 1364561-6

Contextual Info: Part Details for P/N: 1-1364561-1 Products | Catalog | Brands | Industries | Commerce | Supplier | Contact Us | About | Home Home Part Number Search Document Search Cable Assemblies and Interface Devices Cable Assemblies AMP 1-1364561-1 Active Active Tyco Electronics P/N: 1-1364561-1

Contextual Info: C orporate Hom e | Electronic Components | Se gm e nts | W ho W e Are My Account Searc h Products Documentation Resources My Account Customer Support Home > Products > By Type > Socket/C ard Products > Product Feature Selector > Product Details 1-1364990-4 Product Details

Contextual Info: This document was generated on 08/21/2012 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: Status: Overview: Description: 71436-1364 Active PMC 1.00mm Pitch Mezzanine IEEE 1386 Plug, Surface Mount, Dual Row, Vertical Stacking, 64 Circuits, 7.35mm Unmated Height, with PCB Locator Pegs, with Robotic

Silicon Image 1364

Abstract: Video Processors sii1161 PanelLink receiver
Contextual Info: Silicon Image - Product search Home Products PCs and Displays SiI 1364 and SiI 1362 Find a local sales contact: SDVO-DVI PanelLink Transmitter The SiI 1364 and SiI 1362 are the world's first fully compliant Serial Digital Video Output SDVO - Select a country

verilog hdl code for D Flipflop

Abstract: verilog code for static ram 16v8 programming Guide CY3138 16V8 20V8 CY3138R62 CY37256V CY39100V parallel to serial conversion verilog
Contextual Info: CY3138 Warp Enterprise Verilog CPLD Software Features • Verilog IEEE 1364 high-level language compilers with the following features: • VHDL or Verilog timing model output for use with third-party simulators • Active-HDL™ Sim Release 4.1 timing simulation from