1355A1 Search Results

CY7C1357A-100AC

Abstract: CY7C1355A CY7C1357A
Contextual Info: CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 133, 117, and 100 MHz

CY7C1355A

Abstract: CY7C1357A
Contextual Info: CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 133, 117, and 100 MHz

Contextual Info: UNITED MICROELECTRONICS TE J E | 1355-A1E 0D00S03 □ T -5 2 -3 3 -1 9 ^75 UM83C002 RAM Buffer Controller FEATURES PIN CO NFIGU RATION • ■ ■ ■ ■ ■ 3 D M A Channels Host Processor Port Refresh for Dynamic R A M s Built in R A M Access Priority Network