132-PIN QFN Search Results

LC4064V

Abstract: Lattice ispmach LC4064V ispMACH 4A5 flip chip bga 0,8 mm OR3T80 LC4064 OR3C80 OR3T20 OR3T30 OR3T55
Contextual Info: Lattice Package Offering Packages shown actual size. All dimensions refer to package body size. 32-Pin QFN 5 x 5 mm 0.5 mm pitch 6 x 6 mm 0.5 mm pitch 23 x 23 mm 1.0 mm pitch 27 x 27 mm 1.27 mm pitch 100-Ball fpBGA 132-Ball csBGA 56-Ball csBGA 11 x 11 mm 1.0 mm pitch

AT90SCR200

Abstract: AT90SCR200H Programming Bootloader at90scr200 At90scr AT90SCR200LHS ISO7816-12 Programming Bootloader at90scr100 AT90SCR200LSD AT90SCR100 Inside Secure
Contextual Info: TPR0327C Technical Datasheet Preliminary AT90SCR100/116/132/200 2 TPR0327C – VIC – 23Jan12 AT90SCR100/116/132/200 Table of Contents General 1 Block Diagram .13

Contextual Info: TPR0327B Technical Datasheet Preliminary AT90SCR100/116/132 2 TPR0327B – VIC – 16Fev11 AT90SCR100/116/132 Table of Contents General 1 Block Diagram .13

2 way video splitter circuit diagram

Abstract: TV 4 way splitter, circuit diagram TV 3 way splitter, circuit diagram TV 2 way splitter circuit diagram ,2 way video splitter circuit diagram 2 way tv splitter circuit diagram 2 way video splitter circuit "3 way splitter", circuit diagram APS3607 active Splitter
Contextual Info: APS3607 Four-way Active Power Splitter aDVANCED PRODUCT INFORMATION - Rev 0.2 FEATURES • Single Input, Quadruple Output Design • Wideband Operation to above 1 GHz • Nominal 3.2 dB Gain • 4.7 dB Typical Noise Figure AP • Single +3.3V or +5V Supply

MM232R

Abstract: FT232RQ RS232 TTL self powered FT232Rs CLK48 FT232BM FT232R FT232RBitBangModes CMOS RS232 Level Converter to 2.8V FT232RB
Contextual Info: Future Technology Devices International Ltd MM232R USB - Serial UART Development Module Datasheet Document Reference No.: FT_000214 Version 1.1 Issue Date: 2010-03-12 Future Technology Devices International Ltd FTDI Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow, G41 1HH, United Kingdom

Contextual Info: TGC4408-SM 18 - 20 GHz Block Downconverter Applications •  4408 VSAT Ground Terminal Millimeter wave Communications 1307 0490 32-pin 5x6mm QFN package Functional Block Diagram 32 General Description The TGC4408-SM provides a differential signal at 1/4th the VCO frequency for use in a phase-locked

Contextual Info: PSoC 3: CY8C32 Automotive Family Datasheet Programmable System-on-Chip PSoC® General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip while being AEC-Q100 compliant. The CY8C32 family offers a modern method

Contextual Info: APS3628 Eight-way Active Power Splitter PRELIMINARY DATA SHEET- Rev 1.0 FEATURES • Single Input, Eight Output Design • Wideband Operation to above 1 GHz • Nominal 4.2 dB Gain • 4 dB Typical Noise Figure • Single +3.3 V Supply APS 362 • High Linearity, Low Distortion

HS350

Abstract: NE696M01 VP215 K3140
Contextual Info: DATA SHEET BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT µPB1008K REFERENCE FREQUENCY 27.456 MHz, 2ndIF FREQUENCY 132 kHz RF/IF FREQUENCY DOWN-CONVERTER + PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER DESCRIPTION The µPB1008K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion

Contextual Info: Future Technology Devices International Ltd MM232R USB - Serial UART Development Module Datasheet Document Reference No.: FT_000214 Version 1.1 Issue Date: 2010-03-12 Future Technology Devices International Ltd FTDI Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow, G41 1HH, United Kingdom

Contextual Info: PSoC 3: CY8C32 Automotive Family Datasheet Programmable System-on-Chip PSoC® General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip while being AEC-Q100 compliant. The CY8C32 family offers a modern method

rf 4*4 mm QFN

Abstract: APS3628RS34P
Contextual Info: Not recommended for new designs APS3628 Eight-way Active Power Splitter PRELIMINARY DATA SHEET- Rev 1.2 FEATURES • Single Input, Eight Output Design • Wideband Operation to above 1 GHz • Nominal 4.2 dB Gain • 4 dB Typical Noise Figure • Single +3.3 V Supply

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.2, September 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-256 pinout

Abstract: LCMXO2-2000 pinout
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.1, June 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: TGC4408-SM 18 - 20 GHz Block Downconverter Applications • • 4408 VSAT Ground Terminal Millimeter wave Communications 1217 1087 32-pin 5x6mm QFN package Functional Block Diagram 32 30 29 28 The TriQuint TGC4408-SM is a low cost Ku band downconverter. It provides in a single package a

MACHXO2 7000 pinout

Abstract: MachXO2-4000
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.3, December 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.1, June 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

HS350

Abstract: NE696M01 VP215 K3140
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

GRM155R71H101KA01D

Abstract: 1869DH murata new year date code
Contextual Info: APS3625 5-Way Active Splitter with One-Port Bypass 50 MHz to 1000 MHz Preliminary Data sheet - Rev 1.1 FEATURES • Single Input, 5-way Output • Wideband Operation: to Above 1 GHz • Maintains RF signal path to high priority port “Phone” in power loss mode

Contextual Info: PSoC 3: CY8C34 Family Datasheet ® Programmable System-on-Chip PSoC General Description PSoC® 3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 3 architecture boosts performance through:

APS3611

Abstract: tv tuner cards moca filter moca filter catv moca ANADIGICS
Contextual Info: APS3611 870 GHz Two-way Active Power Splitter Optimized for MOCA-Enabled Subscriber equipment PRELIMINARY DATA SHEET - Rev 1.1 FEATURES • Single Input, Double Output Design • Gain profile compensates for inband MOCA line filter attenuation • Wideband Operation to 870 MHz

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 2.5, May 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: TGC4408-SM 18 - 20 GHz Block Downconverter Applications • • 1 4408 VSAT Ground Terminal Millimeter wave Communications 1217 1087 32-pin 5x6mm QFN package 1 1 Functional Block Diagram 1 General Description1 31 30 29 28 Subharmonic Mixer LNA GND 1 25 GND

LCMX02 1200

Abstract: LCMX02 LCMX02 256 LCMX02 640 MACHXO2 1200 pinout file LCMXO2-1200HC-4MG132C MACHXO2 7000 pinout file MACHXO2-1200ZE LCMXO2-7000 LCMXO2-2000
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 01.8, March 2012 MachXO2 Family Data Sheet Introduction March 2012 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only