128K MEMORY RAM Search Results

Contextual Info: AK632128W/AK632128Z 128K x 32 SRAM MODULE ACCUTEK MICROCIRCUIT DESCRIPTION The Accutek AK632128 high density memory module is a static random access memory organized in 128K x 32 bit words. The assembly consists of four high speed 128K x 8 SRAMs in surface

003FE

Abstract: 9l reset CY7C0831V CY7C0832V CY7C0851V CY7C0852V KRE 101 2003
Contextual Info: CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation

Contextual Info: _ CY7C008/009 CY7C018/019 s ->«a " p Y p - 64K/128K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location • 64K x 8 organization CY7C008 • 128K x 8 organization (CY7C009)

mcr 72 hpm 06

Abstract: NFA 222 nfa 102 x0506 counter up/down ternary content addressable memory NL82721 CBUS63-CBUS0 053X0 3702c
Contextual Info: NL82721 IPCAM-1 1Kx128 128K Ternary Synchronous Content Addressable Memory (IPCAM) Description The NL82721 is a 128K bit Ternary Synchronous Content Addressable Memory. The NL82721 device performs high-speed parallel search operations on memory tables. Its primary application is as an address filter or an address translator for Fast

NL82721-33

Abstract: nfa 223 Select 642 UX nfa 102 NL82721 ipcam Ternary CAM "routing tables" X0502 NFA 222
Contextual Info: NL82721 IPCAM-1 1Kx128 128K Ternary Synchronous Content Addressable Memory (IPCAM) Description The NL82721 is a 128K bit Ternary Synchronous Content Addressable Memory. The NL82721 device performs high-speed parallel search operations on memory tables. Its primary application is as an address filter or an address translator for Fast

saa 1291

Abstract: CY7C008 CY7C009 CY7C018 CY7C019 IDT7008
Contextual Info: iJë- CY7C008/009 CY7C018/019 : CYPRESS PRELIMINARY 64K/128K x 8/9 Dual-Port Static RAM Features True Dual-Ported memory cells which allow sim ulta­ neous access of the same memory location 64K x 8 organization CY7C008 128K x 8 organization (CY7C009) 64K x 9 organization (CY7C018)

error multiplexer parity comparator

Abstract: PQFP144 ST10 ST10F269 TQFP144 1221h ST10F269 03 st10 Bootstrap p46a
Contextual Info: ST10F269Zx 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET • ■ 128K or 256KByte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM 16 16 8 16 Interrupt Controller 8 Por t 5 16 BRG BRG

Contextual Info: DS2251/T PRODUCT PREVIEW DS2251 128K Micro Stik DALLAS SEMICONDUCTOR FEA TU R ES PIN DESCRIPTION • Up to 128K of nonvolatile SRAM onboard for program and data memory • Bytewide address and data bus leaves port pins available • Three peripheral enables memory map

Contextual Info: □PM DPE41288 Dense-Pac Microsystems. Inc. 128K X 8 CMOS EEPROM MODULE O DESCRIPTION: The DPE41288 is a high-performance Electrically Erasable and Programmable Read O nly Memory EEPROM module organized 128K X 8. The DPE41288 is pin compatable with the JEDEC Standard for 128K X 8 SRAM Monolithic devices.

Contextual Info: D P E 4 1 2 8 8 128K X 8 CMOS EEPROM MODULE DESCRIPTION: The DPE41288 is a high-performance Electrically Erasable and Programmable Read Only Memory EEPROM module organized 128K X 8. The DPE41288 is pin compatable with the JEDEC Standard for 128K X 8 SRAM Monolithic devices.

A81L801

Abstract: 69LD
Contextual Info: A81L801 Stacked Multi-chip Package MCP 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM Preliminary Document Title Stacked Multi-chip Package (MCP) 1M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM

CY62128BNLL-70SXI

Abstract: CY62128BNLL-70ZXC CY62128BN CY62128BNLL-55SC CY62128BNLL-55SI CY62128BNLL-55SXC
Contextual Info: CY62128BN MoBL 1-Mbit 128K x 8 Static RAM Functional Description[1] Features • Temperature Ranges The CY62128BN is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active

CY62128BN

Abstract: CY62128BNLL-55SXI CY62128BNLL-55ZXI CY62128BNLL-70SXA
Contextual Info: CY62128BN MoBL 1-Mbit 128K x 8 Static RAM Functional Description[1] Features • Temperature Ranges The CY62128BN is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active

CY62128BN

Abstract: CY62128BNLL-55SC CY62128BNLL-55SI CY62128BNLL-55SXC
Contextual Info: CY62128BN MoBL 1-Mbit 128K x 8 Static RAM Functional Description[1] Features • Temperature Ranges The CY62128BN is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active

BW206

Contextual Info: 128K x 36, 256K x 18, 3.3V SYNCHRONOUS SRAMS WITH ZBT FEATURE, BURST COUNTER AND FLOW-THROUGH OUTPUTS PRELIMINARY IDT71V2557JDT71V2559 IDT71V3557, IDT71V3559 FEATURES: • 128K x 3 6,256K x 18 memory configurations. • Supports high performance system speed -100 MHz

IDT71V2576

Abstract: IDT71V2578 IDT71V3576 IDT71V3578 71V2578
Contextual Info: Integrated Device Technology, Inc. 128K x 36, 256K x 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, PIPELINED OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT PRELIMINARY IDT71V2576 IDT71V2578 IDT71V3576 IDT71V3578 FEATURES: DESCRIPTION: • 128K x 36, 256K x 18 memory configurations

Contextual Info: Integrateci DeviceTechnology, Inc. 128K x 36, 256K x 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, FLOW-THROUGH OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT PRELIMINARY IDT71V2577 IDT71V2579 IDT71V3577 IDT71V3579 FEATURES: DESCRIPTION: • 128K x 36, 256K x 18 memory configurations

Contextual Info: Integrated Device Technology, Inc. 128K x 36, 256K x 18, 3.3V SYNCHRONOUS SRAMS WITH 2.5V I/O OPTION, PIPELINED OUTPUTS, BURST COUNTER, SINGLE CYCLE DESELECT PRELIMINARY IDT71V2576 IDT71V2578 IDT71V3576 IDT71V3578 FEATURES: DESCRIPTION: • 128K x 36, 256K x 18 memory configurations

5C100B-25

Abstract: 5C1008-25 20D14 5C100B
Contextual Info: SMJ5C1008 128K BY 8-BIT STATIC RANDOM-ACCESS MEMORY _ SQMS734A - MAY 1996 - REVISED JUNE 1997 Processed to MIL-PRF-38535 Organization . . . 128K Words x 8 Bits Fast Static Operation Single 5-V Supply ±10% Tolerance Maximum Access Time From Address or

256FBGA

Abstract: CYD01S18V CYD02S18V CYD04S18V CYD09S18V
Contextual Info: CYD01S18V/CYD02S18V CYD04S18V/CYD09S18V PRELIMINARY FLEx18 3.3V 64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation

Contextual Info: 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V3576S IDT71V3578S IDT71V3576SA IDT71V3578SA Description 128K x 36, 256K x 18 memory configurations

71V25761

Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V25761S IDT71V25781S IDT71V25761SA IDT71V25781SA Description 128K x 36, 256K x 18 memory configurations

Contextual Info: Preliminary W29F201 128K X 16 CMOS FLASH MEMORY G E N E R A L D E S C R IP T IO N The W29F201 is a 2-megabit, 5-volt only CMOS tlash memory organized as 128K x 16 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt Vpp is

ba6l

Abstract: BA5L BA4L
Contextual Info: HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 36 banks – 4 megabits of memory on chip