1280T Search Results

Contextual Info: CRO Product Specification Model: CRO190-1280T Rev: P2 Date: 10/27/2004 Customer: SIRENZA MICRODEVICES Operating Temperature Range: Parameter Min Frequency Range - Typ 1240 Max Units X 1320 MHz X -40 ° to 85 ° C Remarks Tuning Voltage: 1240 MHz 1 1.5 1320 MHz

qs-280

Abstract: 74FCT280 ZIP15 74FCT280T ZIP-15
Contextual Info: QS280T, 1280T Q S 5 4 /7 4 F C T 2 8 0 T High Speed CMOS 9-Bit Parity G enerator/Checker Q Q S 5 4 /7 4 F C T 1 2 8 0 T F E A TU R E S /B E N E FIT S • • • • • QSFCT280BT faster than FAST 1280T has 18 enable, registered outputs lol=48 mA COM, 32 mA MIL

74FCT128

Contextual Info: QSFCT280T, Q 1280T QS54/74FCT280T High Speed CMOS 9-Bit Parity Generator/Checker QS54/1280T FEATURES/BENEFITS • • • • • QSFCT280BT faster than FAST 1280T has 18 enable, registered outputs lol=48 mA COM, 32 mA MIL TTL-compatible input and output levels

Contextual Info: QSFCT280T, 1280T High Speed C M O S q s 5 4 /7 4 f c t 2 8 o t 9-Bit Parity q s 5 4 / 7 4 f c t i 2 8 ot G enerator/Checker FEA TU R E S/B EN EFIT S • • • • • 6.3 ns delay, I x to Xe for QSFCT280BT 2 ns setup, Ix to reg clock for QSFCT1280BT QSFCT280BT faster than FAST

1280T

Contextual Info: QS280T, Q 1280T QS54/74FCT280T High Speed CMOS 9-Bit Parity G enerator/C hecker QS54/1280T FEATURES/BENEFITS • • • • • QSFCT280BT faster than FAST 1280T has 18 enable, registered outputs lol=48 mA COM, 32 mA MIL TTL-compatible input and output levels

FCT1280

Abstract: 072AC 74FCT128
Contextual Info: QSFCT280T, 1280T e High Speed CMOS 9-Bit Parity Generator/Checker qs54/74fct28ot q s 54/74f c t i 2bot FEATURES/BENEFITS • QSFCT280BT faster than FAST • 1280T has 18 enable, registered outputs • Io l = 48 mA COM, 32 mA MIL • TTL-compatible input and output levels

Contextual Info: ÖUALITY SEMICONDUC TOR INC bSE J> QSFCT280T, B 74fc,bfl03 ÜGD1EG3 417 1280T High Speed CMOS 9-Bit Parity Generator/Checker q s 54/74 f c t 2 sot qs54/74fcti28ot FEATURES/BENEFITS • • • • • QSFCT280BT faster than FAST 6.3 ns delay, I x to Xe for QSFCT280BT

74FCT280

Abstract: ZIP7
Contextual Info: QS280T, ô 1280T QS54/74FCT280T High Speed CMOS 9-Bit Parity G enerator/C hecker QS54/1280T FEATURES/BENEFITS • • • • • QSFCT280BT aster than FAST 1280T has 18 enable, registered outputs lol=48 mA COM, 32 mA MIL TTL-compatible input and output levels

Contextual Info: QSFCT280T, 1280T High Speed CMOS 9-Bit Parity Generator/Checker Q q ss4/ 74f c t 28o t qs54/74fcti28ot FEATURES/BENEFITS • QSFCT280BT faster than FAST • 1280T has 18 enable, registered outputs • I o l = 48 mA COM, 32 mA MIL • TTL-compatible input and output levels

c714 diode

Abstract: FCT1280
Contextual Info: QSFCT280T, 1280T Q H ig h S p e e d C M O S q s 54/ 7 4 f c t 28o t 9 -B it P a r ity G e n e r a to r /C h e c k e r q s 5 4 /7 4 f c t i28ot FEATURES/BENEFITS • QSFCT280BT faster than FAST • 1280T has 18 enable, registered outputs • I o l = 48 mA COM, 32 mA MIL

AT91SAM3U4

Abstract: at91sam3 1N1308 MAR 735 REGULATOR IC 7912 pin identify AT91SAM3U4E SAM3u1 AT91SAM3U 3961 G.E 0x20180
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

Contextual Info: FUJITSU SEMICONDUCTOR CM25-10150-2E CONTROLLER MANUAL F2MCTM-8L 8-bit Microcontroller MB89210 Series Hardware Manual F2MCTM-8L 8-bit Microcontroller MB89210 Series Hardware Manual FUJITSU LIMITED Preface • Purpose of this document and intended reader We sincerely thank you for your continued use of Fujitsu semiconductor products.

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

Contextual Info: STw8009 STw8019 Mobile video DENC Features • Two analog outputs 10 bits DAC with: – CVBS (Composite) output or Y/C (S-VHS) – NTSC-J, M & 4.43 & PAL-BDGHI, N, Nc, M support – 35 mA current driver ■ 8-bit digital interface input supporting both embedded and external synchro

AT91SAM9M11

Abstract: VC 5022 emmc bga 162 EN 50156-1 schematic diagram of ip camera sensor H.264 encoder chip 2012 cmos 4000 logic book eMMC 4.51 charge battery 4060 4X4 push-button matrix keyboard
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • • – 4-port, 4-bank DDR2/LPDDR Controller – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

Contextual Info: SAM9M10 Atmel | SMART ARM-based Embedded MPU DATASHEET Description The Atmel | SMART SAM9M10 is a multimedia-enabled mid-range ARM926based embedded MPU running at 400MHz, combining user interfaces, video playback and connectivity. It includes hardware video decoder, LCD Controller,

rx706

Abstract: duplex led display alarm clock TMS 3451 MATERIAL INSPECTION checklist, PCB EP 613 power supply 923 54 06 ng abs atmel 935 121-972 magnetic card reader SCHEMATIC msr 605
Contextual Info: Features • Core • • • • • • – ARM Cortex -M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

BA 49181

Abstract: AT91SAM9G45b AT91SAM9G45B-CU TD 346 sam9g45 atmel 935 TA 49181 49110 NR 3M EMC Products se 047 equivalent
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static

AT91SAM3U4

Abstract: STR 6653 ITE 8512 SAM3u AT91SAM3U LT 725 integrated circuit scl 1058 AT91SAM3U4E AD12Bx 131194
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

TSL1410

Abstract: TSL1410R
Contextual Info: TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD r r D D D D D D D D D D D TAOS043E − APRIL 2007 1280 × 1 Sensor-Element Organization 400 Dot-Per-Inch DPI Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground

ATSC/NTSC

Abstract: CCIR Report 624-4 digital cvbs pattern 146T ITU-R601 ITU-R625 1888T
Contextual Info: IMPORTANT NOTICE Dear customer, As from February 2nd 2009, ST and Ericsson have merged Ericsson Mobile Platforms and ST-NXP Wireless into a 50/50 joint venture "ST‐Ericsson". As a result, the following changes are applicable to the attached

Contextual Info: TSL1410 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD t t TAOS011 – DECEMBER 1999 D 1280 × 1 Sensor-Element Organization D 400 Dot-Per-Inch DPI Sensor Pitch D High Linearity and Low Noise for 256 (TOP VIEW) Gray-Scale Applications Output Referenced to Ground

Contextual Info: TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD r r D D D D D D D D D D D TAOS043A - DECEMBER 2003 1280 × 1 Sensor-Element Organization 400 Dot-Per-Inch DPI Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground

1888T

Abstract: ITU-R601 146T
Contextual Info: 34 .807IRELESS IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. ● Company name - STMicroelectronics NV is replaced with ST-NXP Wireless.