128 K DATA SHEET Search Results

Contextual Info: FM28V100 1-Mbit 128 K x 8 F-RAM Memory 1-Mbit (128 K × 8) F-RAM Memory Features • 1-Mbit ferroelectric random access memory (F-RAM) logically organized as 128 K × 8 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (see the Data Retention and

Contextual Info: FM28V100 1-Mbit 128 K x 8 F-RAM Memory Features • 1-Mbit ferroelectric random access memory (F-RAM) logically organized as 128 K × 8 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table)

Contextual Info: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features January 2004 • 32,768 channel x 32,768 channel non-blocking digital TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking

ZL50074

Abstract: STOD03 Motorola P13 - 02.08.00
Contextual Info: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features January 2004 • 32,768 channel x 32,768 channel non-blocking digital TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking

ad5255

Contextual Info: a 3-Channel, Dual 512 and Single 128 Position Digital Potentiometer with Nonvolatile Memory Preliminary Technical Data FEATURES 3-Channel: Dual, 512-Position Single 128-Position 25 kΩ, 250 kΩ Low Temperature Coefficient - 35ppm/°C Nonvolatile Memory1 Preset Maintains Wiper Settings

ZL50074

Abstract: ZL50074GAC
Contextual Info: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features July 2004 • 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking

Contextual Info: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features March 2004 • 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking

Contextual Info: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features April 2005 • 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking

ZL50074

Abstract: ZL50074GAC ZL50074GAG2
Contextual Info: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features • January 2006 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking

Contextual Info: ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Features August 2005 • 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex TDM switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking

AD5255

Abstract: 200H AD5255BRU25 AD5255BRU250 AD5255BRU25-RL7 ADN2860 zener diode having 11 volts
Contextual Info: a 3-Channel, Dual 512 and Single 128 Position Digital Potentiometer with Nonvolatile Memory AD5255 Preliminary Technical Data FEATURES 3-Channel: Dual, 512-Position Single 128-Position 25 kΩ, 250 kΩ Low Temperature Coefficient - 35ppm/°C Nonvolatile Memory1 Preset Maintains Wiper Settings

Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-Through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-Through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

CY7C1351G

Abstract: CY7C1351G-100AXC
Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture Features Functional Description • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-Through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-Through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture Functional Description Features • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

CY7C1351G

Abstract: CY7C1351G-100AXC
Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture Features Functional Description • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture Features Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture Features Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

Contextual Info: CY7C1351G 4-Mbit 128 K x 36 Flow-Through SRAM with NoBL Architecture 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Can support up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock

ZL50073

Contextual Info: ZL50073 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams 8, 16, 32 or 64 Mbps , and 128 Inputs and 128 Outputs Data Sheet Features • January 2004 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at

Contextual Info: Data Sheet, Rev. 0.5, Jan. 2004 HYS72D32300GBR–[5/6]–C HYS72D64300GBR–[5/6]–C HYS72D[128/64]320GBR–5–C HYS72D[128/64]320GBR–6–C 184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g .

STiD12

Contextual Info: ZL50073 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams 8, 16, 32 or 64 Mbps , and 128 Inputs and 128 Outputs Data Sheet Features • January 2004 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at

cd 40188

Abstract: SToD31 STiD12 SToD15 40107 ZL50073 ZL50073GAC ZL50073GAG2 FPI02 40107 Equivalent
Contextual Info: ZL50073 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams 8, 16, 32 or 64 Mbps , and 128 Inputs and 128 Outputs Data Sheet Features • January 2006 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at