122NS Search Results

transistor ad P44

Abstract: MN1020407 QFP084-P-1818E N10204 AD6 transistor
Contextual Info: □ MN1020407 • Type M N 1020407 [ES Engineering Sam ple is availab le] 1 ROM (x8-bit) 32K (External m e m ory cannot be expanded) 1 RAM (x8-bit) 1 K (External m e m o ry cannot be expanded) 1 Minimum Instruction Execution Time Interrupts 122ns (at 4 .5 to 5 .5 V , 1 6 .3 9 M H z )

PD4A

Contextual Info: _ bq3285 UIMITRODE- Real-Time Clock RTC Features >• Direct clock/calendar replace­ ment for IBM AT-compatible computers and other applications >- Functionally compatible with the DS1285 ~ Closely matches MC146818A pin configuration >• 114 bytes of general nonvolatile

MT90812AL1

Abstract: TGE-5 EB32
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Mar 2011 Features • • • • • • • • • • • • • • • • • • MT90812AP MT90812AL MT90812APR MT90812AP1 MT90812AL1 MT90812APR1 192 channel x 192 channel non-blocking switching

LCD TV SCHEMA

Abstract: srf 2497 lcd panel schema LC5812 LC5812H QIP80A light transistor EVA-510 V552 EVA510
Contextual Info: Ordering number: EN2058A CMOS LSI LC 5 8 1 2 NO .2058A SAHYO r i 4-Bit M icrocom puter w ith Internal LCD Driver The LC5812 series models are 4-bit, single-chip, high-performance microcomputers equipped with LCD drivers. They are produced by CMOS technology. Their numerous features include

74HC12

Abstract: ST-BUS MH89760B MH89790B MT8920B MT8920BE MT8920BP MT8920BS MT8976 MT8979
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8920B ST-BUS Parallel Access Circuit  Features • • • • • • • • ISSUE 7 High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP mode 1 Fast dual-port RAM access (mode 2) Access time: 120 nsec

MEB90812

Abstract: WARBLE TONE GENERATORS intel 8247 circuit diagram of car central lock system conference system MT8952 MT8952B MT90812 MT90812AL MT90812AP
Contextual Info: MT90812 Integrated Digital Switch IDX Advance Information Features • • • • • • • • • • • • • • • • • • 192 channel x 192 channel non-blocking switching 2 local bus streams @ 2Mb/s supports up to 64 channels In TDM mode, the expansion bus supports up

siemens Logo 230 rc manual

Abstract: GR-1244-CORE MT9044 MT9044AL MT9044AP TR62411
Contextual Info: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features November 2003 • Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces

BQ3287A

Contextual Info: bq3287/bq3287A BENCHM ARQ Real-Time Clock RTC Module Features >• Direct clock/calendar replacement for IBM AT-compatible computers and other applications >• Functionally compatible with the DS1287/DS1287A and MC146818A > 114 bytes of general nonvolatile

ST10Nm

Abstract: 32000K
Contextual Info:  STLC5465B MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR

RG703

Abstract: ch8c ch6b Motorola LSC microcontroller DS26528 DS26521 DS26522 DS26524 DS26524GN 1103h
Contextual Info: DS26524 Quad T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26524 is a single-chip 4-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

20EF TRANSFORMER

Abstract: TRANSFORMER 20EF 20F9 rexton AAIS mark csc 9102 D3318
Contextual Info: PRODUCT PREVIEW GENERAL DESCRIPTION The DS26519 is a single-chip 16-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines. The DS26518 is a 8-port SCT. The DS26514 is a 4-port

11290

Abstract: TLS14
Contextual Info: DS26528 Octal T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26528 is a single-chip 8-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

V20K 275

Abstract: V20K V10K
Contextual Info: PRELIMINARY TECHNICAL DATA a Differential Input, 1MSPS, 12- & 10-Bit ADCs in 8-lead SOT-23 Preliminary Technical Data FEATURES Fast Throughput Rate: 1MSPS Specified for VDD of 3 V and 5 V Low Power at max Throughput Rate: 3.75 mW typ at 1MSPS with 3 V Supplies

Contextual Info: CMOS 4-Bit Single-Chip Microcomputers LC5860/5870 Series Overview T he LC 58 60/5 870 S eries C M O S 4-b it sin gle -chip m icro­ com p uters are ideal for con tro lling LC D displays. S anyo's pro prie ta ry LCD display circu it te ch n o lo g y con tro lle r/

TLS14

Contextual Info: DS26528 Octal T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26528 is a single-chip 8-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul

Contextual Info: N E C E LECTRONI CS INC • fc.7E D fc.427555 QQ3T5Q3 7 2R * N E C E fiPD78002Y Family pPD78001 BY/002BY/P014Y 8-Bit, K-Series Microcontrollers General Purpose With I2C Bus NEC NEC Electronics Inc. Preliminary_ September 1993 Description

mr4040

Abstract: sma e1017 BT 2323 AUDIO CONTROLLER PIN DETAILS ADSP-2199x dc geared motor 60 rmp ADSP-2100 ADSP-21992 summit-ICE ASY 48 VI IC tda 2151
Contextual Info: Preliminary ADSP-2199x Mixed Signal DSP Controller Hardware Reference Preliminary Revision 0, 2003 Part Number: 82-000640-01 Analog Devices, Inc. Digital Signal Processor Division One Technology Way Norwood, Mass. 02062-9106 Preliminary Copyright Information

Contextual Info: EPSON I Overview The RTC-65271 is a real-time clock that was developed as a peripheral IC for AT-compatible computers. The RTC-65271 has a built-in 32.768kHz crystal. Other functions include a calendar year, month, day and day of the week , clock (hours, minutes, seconds), selection of 12-hour or 24-hour timekeeping, automatic leap year adjustment,

T9042

Abstract: 20Ulpp
Contextual Info: MT9042C MITEL M ultitrunk System Synchronizer S E M IC O N D U C T O R Advance Information Features DS5144_ISSUE 1_ April 1999 O rdering Inform ation • Meets jitte r requirem ents for: AT&T T R 6 2 4 1 1 Stratum 3, 4 and S tratum 4 Enhanced tor DS1

Contextual Info: DS26519 16-Port T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26519 is a single-chip 16-port framer and line interface unit LIU combination for T1, E1, and J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines. The

Contextual Info: M ic r o c h ip D S P 3 2 C 1 CMOS Digital Signal Processor FEATURES DESCRIPTION • • • • • The DSP320C10 is the first low power CMOS member of the Microchip Technology DSP320 family of digital signal processors, designed to support a wide range of

ECTF

Abstract: 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH LQFP176 ML53812-2 MVIP-90 ML53812
Contextual Info: DATA SHEET O K I N E T W O R K P R O D U C T S ML53812-2 H.100/H.110 CT Bus System Interface and Time-Slot Interchange January 2000 Revision History September 1999 320101-005 Previous Release January 2000 320101-006 Timing tables altered on page 50: “Local Clock and Frame Synchronization Timing”,

TMS 3450

Abstract: GR-1244-CORE GR1244-CORE MT9045 MT9045AN TR62411
Contextual Info: MT9045 T1/E1/OC3 System Synchronizer Advance Information Features • • • • • • • • • • • • • • DS5270 Supports AT&T TR62411 and Bellcore GR1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813 Option 1 clocks for 2048

motorola 6800 8bit hardware architecture

Abstract: 6800 intel microprocessor pin diagram motorola 6800 8bit software architecture AFM8 VCXO 2048khz crystal 68020-16 80C186-16 AFM2 ana61 control unit of 68020
Contextual Info:  STLC5465B MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR