12 SQ 045 JF Search Results

HA170

Abstract: js35
Contextual Info: HARRIS SEMICOND SECTOR 10E D I 4305571 001227a b | HA-5170 gj HARRIS Precision JFET Input Operational Amplifier Features Applications • • • • • • • • • • • Low Offset Voltage. 100 iV Low Offset Voltage D r ift. 2(iV/°C

Contextual Info: ii ii ii ii ii ii ii ii ACT-S128K32 High Speed - 4 iviegamt o k a m iviuiticnip ivioauie . • ■■ A ■ ■ ■ ■ ■ I ■■ I Features ■ ■ ■ ■ ■ ■ ■ 4 Low Power IDT or Samsung CMOS 128K x 8 SRAMs in one MCM

A6160

Abstract: 060A00 HA2-5160
Contextual Info: IS SEtllCOND SECTOR IDE D | 43D5271 DOiaatB *5 | 53 HARRIS H A - 5 1 6 0 /6 2 Wideband, JFET Input High Slew Rate, Uncompensated, Operational Amplifier Applications Features • • • • • • W ide Gain Bandwidth A V > 1 0 . 100MHz

ha-5180

Abstract: HA2-5180 HA-5180-5 HA7-5180 ha5180 HA5180-5 HA25180 application note 555 electrometer 250FA
Contextual Info: H A -5180 !T! HARRIS Low Bias Current, Low Power JFET Input Operational Amplifier M a y 1990 Features A pplications • Ultra Low Bias C u rre n t. 250fA • Electrometer Amplifier Designs • Low Power Supply Current . 0.8mA

ha-5180

Abstract: A5180
Contextual Info: H A -5180 !T! HARRIS Low Bias Current, Low Power JFET Input Operational Amplifier M a y 1990 Features A pplications • Ultra Low Bias C u rre n t. 250fA • Electrometer Amplifier Designs • Low Power Supply Current . 0.8mA

HOA0963-T51

Abstract: HOA0973-N55 SD5421-002 HOA0961-N51 SDP8004-301 HOA1879-012 HOA0973-N51 HOA0973N51 HOA2001-001 SD1420-002
Contextual Info: Sensing and Control ! " = = Sept, 2002 = E-mail:jian.bo.zhou@honeywell.com www.honeywell.com/sensing/ !"#$%& LED mm 1 !" 1 935mm @IF(mA) 2 0.35 0.70 24 24 1.00 0.35 24 24 0.65 1.10 24 24 1.65 0.20 24 24 0.35 0.70 24 24 1.00 0.35 24 24 0.65 1.10 24 18 1.65

Contextual Info: Features Third Generation Programmable Logic Structure - Easily Achieves Gate Utilization Factors of 80 Percent Increased Logic Flexibility - 86 Inputs and 72 Sum Terms Flexible Output Macrocell - 48 Flip-Flops - 2 per Macrocell - 3 Sum Terms - Can Be OR'ed and Shared

Contextual Info: HARRIS SEMICOND SECTOR 10E d | M3G5271 DQ12S3Q b I H C - 5 5 Q2 Â jgj h a r r is sue Subsciber Line Interface Circuit 7 5 '- / / - / 7 Features Description • Monolithic Integrated Device The H arris SLIC incorporates m any o f the BOR SH T fun ction on a single 1C chip. This includes DC battery feed,

Contextual Info: Features Third Generation Programmable Logic Structure - Easily Achieves Gate Utilization Factors of 80 Percent Increased Logic Flexibility - 86 Inputs and 72 Sum Terms Flexible Output Macrocell - 48 Flip-Flops - 2 per Macrocell - 3 Sum Terms - Can Be OR'ed and Shared

HA5141

Abstract: HA3-5141 transistor Bd 458 transistor code 458 055 4060BD
Contextual Info: [g HARRIS H A - 5 1 4 / 1 4 2 / 4 4 S in g le /D u a l/Q u a d U ltra -L o w Power O perational Am plifiers May 1990 Features A pplications • Lo w S u p p ly C u r r e n t .4 5|jA /A m p • P o rta b le In strum ents

28 LEADLESS CHIP CARRIER DWG

Abstract: MS-009-AE
Contextual Info: PACKAGE DIAGRAM OUTLINES LEADLESS CHIP CARRIER DCN REV DESCRIPTION 17 295 05 UPDATE TO STANDARDIZE DRAWING DATE APPROVAL A E NOTES: 2. E UNLES OTHERWISE SPECIFIED; BSC - BASIC LEAD SPACING BETWEEN CENTERS. DWG # SYMBOL MIN A .060 .075 A1 .050 .065 B1 R9 L 20-1

Contextual Info: Features Industry Standard Architecture 12 ns Maximum Pin-to-Pin Delay Zero Power - 25|iA Maximum Standby Power CMOS and TTL Compatible Inputs and Outputs Advanced Electrically-ErasableTechnology - Reprogrammable - 100% Tested Latch Feature Holds Inputs to Previous Logic State

Contextual Info: Features 3.0V to 5.5V Operating Range Advanced Low-voltage, Zero-power, Electrically-Erasable Programmable Logic Device Edge-sensing “Zero” Power Low-voltage Equivalent of ATF22V10CZ “Zero” Standby Power 25 |_iA Maximum Ideal for Battery Powered Systems

1504AS

Contextual Info: Features * High Density, High Performance Electrically Erasable Complex Programmable Logic Device - 64 Macrocells - 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell - 44, 68, 8 4 ,1 0 0 pins - 7 ns Maximum Pin-to-Pin Delay - Registered Operation Up To 100 MHz

Contextual Info: Features • • • • Read Access Tim e - 90 ns Word-wide or Byte-wide Configurable 8-M egabit Flash and Mask ROM Com patable Low Power CMOS Operation - 100 nA Maximum Standby - 50 mA Maximum Active at 5 MHz W ide Selection of JEDEC Standard Packages - 42-Lead 600 mil PDIP

P320S

Abstract: atmel 714
Contextual Info: Features * 3.0V to 5.5V Operation * Industry Standard Architecture - Emulates Many 20-Pin PALs - Low Cost Easy-to-Use Software Tools * High Speed - 10 ns Maximum Pin-to-Pin Delay * Ultra-Low Power - 5 jiA Max. Pin-Controlled Power Down Mode Option - Typical 100 nA Standby

LSE B10 transformer

Abstract: 3 phase GE analog KWH meter FT500 IEC687 LSE B9 transformer IEC103 3.2768MHz Crystal Poly Phase Energy Meter GE digital KWH meter
Contextual Info: Features Fulfills IEC 1036, Class 1 Accuracy Requirements Fulfills IEC 687, Class 0.5 and Class 0.2 Accuracy, with External Temperature Com pensated Voltage Reference Simultaneous Active, Reactive and Apparent Power and Energy Measurement Power Factor, Frequency, Voltage and Current M easurem ent

Contextual Info: Features Advanced, High-speed, Electrically-erasable Programmable Logic Device - Superset of 22V10 - Enhanced Logic Flexibility - Backward Compatible with ATV750B/BL and ATV750/L Software and Hardware Low Power— Edge-sensing “L” Option with 1 mA Standby Current

OP215G

Abstract: OP-215
Contextual Info: OP-215 PM I DUAL PRECISION JFET-INPUT OPERATIONAL AMPLIFIER n 1ret i s ii jiì M u n o iifh iis : FEATURES • • • • • • • • • • • • • tracking and convenience advantages of a dual op-amp configuration. High Slew Rate . 10V/>* Min

Contextual Info: Features Industry Standard Architecture - Emulates Many 20-Pin PALs - Low Cost Easy-to-Use Software Tools High-Speed Electrically-Erasable Programmable Logic Devices - 12 ns Maximum Pin-to-Pin Delay Low Power - 25 |_iA Standby Power CMOS and TTL Com patible Inputs and Outputs

Contextual Info: Features * Industry Standard Architecture - Low Cost Easy-to-Use Software Tools * High-Speed, Electrically-Erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-Pin Delay * Several Power Saving Options Device lcc, Stand-By lcc, Active ATF22V10B 85 mA

Contextual Info: Features Industry Standard Architecture - Emulates Many 20-Pin PALs - Low Cost Easy-to-Use Software Tools High-Speed Electrically-Erasable Programmable Logic Devices - 5 ns Maximum Pin-to-Pin Delay Low Power -1 0 0 |aA Pin-Controlled Power Down Mode Option

Contextual Info: Features Industry Standard Architecture - Emulates Many 24-Pin PALs - Low Cost Easy-to-Use Software Tools High-Speed Electrically Erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-Pin Delay Several Power Saving Options Device lcc, Stand-By lcc, Active

AT49F1025-70VC

Abstract: AT49F1025
Contextual Info: Features • Single Voltage Operation - 5V Read - 5V Reprogramming Fast Read Access Time - 70 ns Internal Program Control and Timer 8K word Boot Block With Lockout Fast Erase Cycle Time -1 0 seconds Word By Word Programming -1 0 ^s/Word Typical Hardware Data Protection