11BO Search Results

RJ45 5E 8P8C

Abstract: 40MM T568B 26awg cable tie
Contextual Info: 6 5 4 2 3 LTR. F 8 - - E (1) - | —1 PI iJ -H=~ - n -1 Î U U REV. DESCRIPTION DATE A FIRST ISSUE 2 0 1 0 .1 1 .1 3 F L+ 3X rA A Ih u tro Pttûh Cabli DIP CAI. SB Cro»C*bte 2SA1K ISQ/IEC 11BOI fexrtro Patch Cubit LTP C&T. DE C n» € d)le 26AÏG ISO/IEC 11801

A115-A

Abstract: C101 SN74GTL2007 26LVTTL
Contextual Info: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard

es1978

Contextual Info: ES56CV-PI / ES56CVH-PI PCI Audio/Modem Solution Data Sheet p r e l im in a r y < ESS Technology, Inc. DESCRIPTION The ES56CV-PI chipset is a highly integrated multimedia solution which brings advanced PCI audio and modem functionality to notebook and desktop systems. The

Contextual Info: TOSHIBA TENTATIVE TC58FVT160/B160FT-85.-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 16-M BIT 2M x 8 BITS / 1M x 16 BITS CMOS FLASH M EM O R Y DESCRIPTION The TC58FVT160/B160 is a 16,777,216 - bit, 3.0-V read-only electrically erasable and programmable

Contextual Info: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD

SN74GTL2107PWRG4

Abstract: A115-A C101 SN74GTL2107
Contextual Info: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω

Contextual Info: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard

Contextual Info: GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator Rev. 05 — 23 December 2009 Product data sheet 1. General description The GTL2107 is a customized translator between dual Xeon processors, GTL−/GTL/GTL+ I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL

Contextual Info: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard

ltc11s

Abstract: TP-003
Contextual Info: LTC 115 0 ±15V Chopper Stabilized Operational Amplifier with Internal Capacitors FCRTURCS DCSCRIPTIOn • High Voltage Operation, ±18V ■ No External Components Required ■ Maximum Offset Voltage 5nV ■ Maximum Offset Voltage Drift 0.05[iV/°C ■ Low Noise 1.8^iVp-p 0.1 Hz to 10Hz

GTL2006

Contextual Info: INTEGRATED CIRCUITS GTL2006 13-bit GTL/GTL+ to LVTTL translator Preliminary data Philips Semiconductors 2002 Nov 06 Philips Semiconductors Preliminary data 13-bit GTL/GTL+ to LVTTL translator GTL2006 FEATURES PIN CONFIGURATION • Operates as a GTL/GTL+ to LVTTL or LVTTL to to GTL/GTL+

GTL2006

Contextual Info: INTEGRATED CIRCUITS GTL2006 13-bit GTL-/GTL/GTL+ to LVTTL translator Preliminary data Philips Semiconductors 2003 May 27 Philips Semiconductors Preliminary data 13-bit GTL-/GTL/GTL+ to LVTTL translator GTL2006 FEATURES PIN CONFIGURATION • Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to to

GTL2006

Contextual Info: INTEGRATED CIRCUITS GTL2006 13-bit GTL-/GTL/GTL+ to LVTTL translator Product data Philips Semiconductors 2003 Dec 18 Philips Semiconductors Product data 13-bit GTL-/GTL/GTL+ to LVTTL translator GTL2006 FEATURES PIN CONFIGURATION • Operates as a GTL-/GTL/GTL+ to LVTTL sampling receiver or

Contextual Info: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω

10BOn

Abstract: GTL2006 GTL2007 GTL2007PW JESD22-A114 JESD22-A115 JESD78 TSSOP28
Contextual Info: GTL2007 13-bit GTL to LVTTL translator with power good control Rev. 01 — 2 June 2005 Product data sheet 1. General description The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals.

AT56C55

Abstract: AT56C55-IL1T Managing the Driver Enable signal for RS-485 TRANSISTOR BC 187 386EX HD64180 Z180 R3000a Performance Semiconductor radiated-emissions PE2010
Contextual Info: Rabbit 3000 Microprocessor User’s Manual 019–0108 • 030815–L Rabbit 3000 Microprocessor User’s Manual Part Number 019-0108 • 030815–L • Printed in U.S.A. 2002–2003 Rabbit Semiconductor • All rights reserved. Rabbit Semiconductor reserves the right to make changes and

Contextual Info: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω

Contextual Info: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 PW PACKAGE TOP VIEW D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard

A115-A

Abstract: C101 SN74GTL2006
Contextual Info: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD

MBCG

Abstract: fujitsu mbcg CG21403 SC472 CG21303 cg212 0D134 MBCG2 CG21103 QFP-196
Contextual Info: FUJITSU MICROELECTRONICS 31E D n 3 7 M cJ7bS 001345S i QFfll January 1990 Edition 1.1 FUJITSU PRODUCT PROFILE CG21 Series 0.8-micron CMOS Gate Arrays DESCRIPTION T h e C G 21 se rie s o f 0 .8 n m C M O S g a te arra y s are c u rre n tly a va ila b le in liv e d e v ic e ty p e s w ith fro m 3 0 K to 10 0 K g a te s . T h re e m ore

Contextual Info: TOSHIBA TENTATIVE TC58FVT160/B160FT-85.-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 16-M BIT 2M X 8 BITS / 1M X 16 BITS CMOS FLASH M EM O R Y DESCRIPTION The TC58FVT160/B160 is a 16,777,216 - bit, 3.0-V read-only electrically erasable and programmable

Contextual Info: SN74GTL2107 12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR www.ti.com SCLS699 – JULY 2006 FEATURES • • • • PW PACKAGE TOP VIEW Operates as a GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+ Translator Series Termination on TTL Output of 30 Ω

A115-A

Abstract: C101 SN74GTL2006
Contextual Info: SN74GTL2006 13ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing to JEDEC Standard JESD

modbus communication using 8051 assembly code

Abstract: modbus 8051 386EX HD64180 Z180 PE2010 modbus inverter TN235 R30 series
Contextual Info: Rabbit 2000 Microprocessor User’s Manual 019–0069 • 070831–P Rabbit 2000 Microprocessor User’s Manual Part Number 019-0069 • 070831–P • Printed in U.S.A. 2002–2007 Rabbit Semiconductor Inc. • All rights reserved. No part of the contents of this manual may be reproduced or transmitted in any form or by any means