11OCT2012 Search Results

Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. C D COPYRIGHT 20 BY - 2 3 20 RELEASED FOR PUBLICATION LOC REVISIONS DIST CE ALL RIGHTS RESERVED. 1 - P 1. DIMENSIONS ARE FOR REFERENCE ONLY. 2 DESCRIPTION LTR G2 G3 DATE DWN APVD ECR-12-017611 11OCT2012 KG DW ECR-13-015710 10OCT2013

Contextual Info: TMP102 www.ti.com SBOS397C – AUGUST 2007 – REVISED OCTOBER 2012 Low Power Digital Temperature Sensor With SMBus /Two-Wire Serial Interface in SOT563 Check for Samples: TMP102 FEATURES DESCRIPTION • • • The TMP102 is a two-wire, serial output temperature

Contextual Info: STT6N3LLH6 N-channel 30 V, 0.021 Ω typ., 6 A STripFET VI DeepGATE™ Power MOSFET in a SOT23-6L package Datasheet - production data Features Type RDS on VDSS max ID PTOT 6A 1.6 W 0.025 Ω (VGS= 10 V) 4 5 6 3 STT6N3LLH6 30 V 1 0.036 Ω (VGS= 4.5 V) SOT23-6L

Contextual Info: STT6N3LLH6 N-channel 30 V, 0.021 Ω typ., 6 A STripFET VI DeepGATE™ Power MOSFET in a SOT23-6L package Datasheet - production data Features Order code VDSS RDS on max ID PTOT 6A 1.6 W 0.025 Ω (VGS= 10 V) 4 STT6N3LLH6 5 6 30 V 3 2 1 0.036 Ω (VGS= 4.5 V)

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS052B – Revised June 2003 The CD4067B and CD4097B types are supplied in 24-lead hermetic dual-in-line ceramic packages F3A suffix , 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR

Contextual Info: TPS54680-EP www.ti.com SGLS212A – OCTOBER 2003 – REVISED OCTOBER 2012 3-V TO 6-V INPUT, 6-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs SWIFT FOR SEQUENCING Check for Samples: TPS54680-EP FEATURES 1 • • 2 • • • •

STTH60W02

Abstract: STTH60W02CW
Contextual Info: STTH60W02C Turbo 2 ultrafast high voltage rectifier Datasheet  production data Features • A1 Ultrafast switching ■ Low reverse recovery current ■ Low thermal resistance ■ Reduces switching losses ■ ECOPACK 2 compliant component ■ Ribbon bonding for more robustness

Contextual Info: TLE202x, TLE202xA, TLE202xB, TLE202xY EXCALIBUR HIGH-SPEED LOW-POWER PRECISION OPERATIONAL AMPLIFIERS SLOS191D − FEBRUARY 1997 − REVISED NOVEMBER 2010 D D D D D D Supply Current . . . 300 A Max High Unity-Gain Bandwidth . . . 2 MHz Typ High Slew Rate . . . 0.45 V/μs Min

Contextual Info: TLE202x, TLE202xA, TLE202xB, TLE202xY EXCALIBUR HIGH-SPEED LOW-POWER PRECISION OPERATIONAL AMPLIFIERS SLOS191D − FEBRUARY 1997 − REVISED NOVEMBER 2010 D D D D D D Supply Current . . . 300 A Max High Unity-Gain Bandwidth . . . 2 MHz Typ High Slew Rate . . . 0.45 V/μs Min

Contextual Info: TS5A2053 SINGLEĆCHANNEL 10ĆW SPDT ANALOG SWITCH WITH ENABLE www.ti.com SCDS183A – JANUARY 2005 – REVISED APRIL 2006 Description Features The TS5A2053 is a single-pole double-throw SPDT analog switch that is designed to operate from 1.65 V to 5.5 V. This device can handle both digital and analog

H.264 encoder cortex a8

Abstract: arm cortex a9 cortex-a9 CMOS Sensor 1080p H.264 60 android mobile MOTHERBOARD CIRCUIT diagram 667 transistor ecb CHINA TV uoc ARm cortexA9 GPIO android mobile circuit diagram "ARM Cortex A9"
Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP

Contextual Info: TLE202x, TLE202xA, TLE202xB, TLE202xY EXCALIBUR HIGH-SPEED LOW-POWER PRECISION OPERATIONAL AMPLIFIERS SLOS191D − FEBRUARY 1997 − REVISED NOVEMBER 2010 D D D D D D Supply Current . . . 300 A Max High Unity-Gain Bandwidth . . . 2 MHz Typ High Slew Rate . . . 0.45 V/μs Min

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS052B – Revised June 2003 The CD4067B and CD4097B types are supplied in 24-lead hermetic dual-in-line ceramic packages F3A suffix , 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR

arm cortex a9

Abstract: H.264 encoder cortex a8 "ARM Cortex A9" cmos digital camera module MMC 4.2 "NOR Flash controller" H.264 codec PD46 Dual-core ARM Cortex-A9 CPU cortex-a9
Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − production data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP