10X10X09 Search Results

Contextual Info: 19-2726; Rev 1; 2/03 3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs ♦ Excellent SFDR and IMD Performance SFDR = 76dBc at fOUT = 40MHz to Nyquist IMD = -85dBc at fOUT = 10MHz ACLR = 73dB at fOUT = 61MHz ♦ 2mA to 20mA Full-Scale Output Current

MAX5633AECB

Contextual Info: 19-2171; Rev 1; 6/02 16-Bit DACs with 32-Channel Sample-and-Hold Outputs _Applications MEMS Mirror Servo Control ♦ Integrated 16-Bit DAC and 32-Channel SHA with SRAM and Sequencer ♦ 32 Voltage Outputs ♦ 0.005% Output Linearity

56us

Abstract: OC192 MAX3953 MAX3953UGK MAX3970 MAX3971A PDO11 VCO at 15GHZ PDO15 PDO14
Contextual Info: 19-2624; Rev 0; 10/02 10Gbps 1:16 Deserializer with Clock Recovery Features ♦ Serial Data Rate: 9.953Gbps/10.3125Gbps ♦ Clock Recovery with 1:16 Demultiplexer ♦ 0.75UIP-P High-Frequency Jitter Tolerance ♦ 16-Bit Parallel LVDS Output ♦ OIF-Compliant Parallel Interface

GORE-89

Abstract: GORE TWINAX CABLE
Contextual Info: 19-2289; Rev 0; 1/02 KIT ATION EVALU E L B A AVAIL 3.2Gbps Quad Adaptive Cable Equalizer with Cable Driver Features ♦ Single 3.3V Operation ♦ Four Independent Equalizers and Drivers ♦ 725mW at 3.3V Typical Power Dissipation ♦ Data Rates Up to 3.2Gbps

MAX3782

Abstract: MAX3782UGK RDAT212 15k resistor
Contextual Info: 19-2268; Rev 2; 1/03 Dual 1.25Gbps Transceiver ♦ CML Interface Exceeds all PECL AC Specifications for 1000Base-SX/LX, GBIC, or SFP Serial Data ♦ Tx Data Retiming with <0.1UI Total Output Jitter as per IEEE802.3z ♦ Rx Data and Clock Recovery with 0.75UI Jitter

equalizer circuit diagram

Abstract: monitor cable diagram 20 band equalizer equalizer diagram and function MAX3800 MAX3802 MAX3802UGK RG179 CML50 madison cable 68 pin
Contextual Info: 19-2289; Rev 0; 1/02 KIT ATION EVALU E L B A AVAIL 3.2Gbps Quad Adaptive Cable Equalizer with Cable Driver Features ♦ Single 3.3V Operation ♦ Four Independent Equalizers and Drivers ♦ 725mW at 3.3V Typical Power Dissipation ♦ Data Rates Up to 3.2Gbps

MAX5886

Abstract: MAX5887 MAX5888 MAX5888AEGK MAX5888EGK
Contextual Info: 19-2726; Rev 2; 3/03 3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 76dBc at fOUT = 40MHz to Nyquist IMD = -85dBc at fOUT = 10MHz ACLR = 73dB at fOUT = 61MHz

Contextual Info: 19-2268; Rev 0; 3/02 Dual 1.25Gbps Transceiver ♦ CML Interface Exceeds all PECL AC Specifications for 1000Base-SX/LX, GBIC, or SFP Serial Data ♦ Tx Data Retiming with <0.1UI Total Output Jitter Beats IEEE802.3z Requirements ♦ Rx Data and Clock Recovery with 0.75UI Jitter

MAX3782

Abstract: MAX3782UGK RDAT212 SFP LVDS RX1 receiver
Contextual Info: 19-2268; Rev 1; 5/02 Dual 1.25Gbps Transceiver ♦ CML Interface Exceeds all PECL AC Specifications for 1000Base-SX/LX, GBIC, or SFP Serial Data ♦ Tx Data Retiming with <0.1UI Total Output Jitter as per IEEE802.3z ♦ Rx Data and Clock Recovery with 0.75UI Jitter