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Catalog Datasheet	Type	Document Tags	PDF
1006es Abstract: CS01 CS02 EDR-7320 MS-001 ATtiny12L-4SU ATtiny12-8SU Contextual Info: Features • Utilizes the AVR RISC Architecture • High-performance and Low-power 8-bit RISC Architecture • • • • • • • • – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz	Original	ATtiny12) ATtiny11/12) ATtiny12 1006ES CS01 CS02 EDR-7320 MS-001 ATtiny12L-4SU ATtiny12-8SU	PDF

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1006es

Abstract: CS01 CS02 EDR-7320 MS-001 ATtiny12L-4SU ATtiny12-8SU
Contextual Info: Features • Utilizes the AVR RISC Architecture • High-performance and Low-power 8-bit RISC Architecture • • • • • • • • – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz

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ATtiny12) ATtiny11/12) ATtiny12 1006ES CS01 CS02 EDR-7320 MS-001 ATtiny12L-4SU ATtiny12-8SU

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