10-35 V3 Search Results

Contextual Info: SPECIAL APPLICATION AMPLIFIERS pRFfji.JFr ‘ ‘ -I H A NCM. DC d jw f r r-u'jnr 'JU M H h - ' 3ff 35 5 ’2 6 6 H T r^ 15 15 15 15 45 75 35 35 * 7 2 3 1 1 1.5 1.5 1.5 1.5 5.0 8 8 10 10 17 15 15 15 15 15 50 50 75 95 95 2 8 3 4 1 5 5 8 17 1B 1.8 18 18 2.5

Contextual Info: Double-Balanced Mixer M2A/M2AC V3 Features • • • • • Product Image LO 10 to 1500 MHz RF 10 to 1500 MHz IF DC to 800 MHz LO Drive +7 dBm nominal High Isolation 35 dB (typ) Description The M2A is a double balanced mixer, designed for use in military,

Contextual Info: E-Series 2-Way 0° Power Divider 1 - 200 MHz ES-2-2-75 V3.00 R-2 Features ● ● 2 Way 0° Specifications @ 25°C Frequency Range 1 - 200 MHz Insertion Loss 1 -200 MHz Typical 0.2 dB Maximum 0.5 dB Isolation 1 -10 MHz 10 - 100 MHz 100 - 200 MHz Typical 35 dB

A19 transistor

Abstract: A19-1 CA19-1 SMA19-1
Contextual Info: Cascadable Amplifier 10 to 1000 MHz A19-1 / SMA19-1 V3 Features Product Image • HIGH OUTPUT POWER: +22.5 dBm TYP. • HIGH THIRD ORDER I.P.: +35 dBm (TYP.) • MEDIUM NOISE FIGURE: 6.0 dB (TYP.) Description The A19-1 RF amplifier is a discrete thin film hybrid design,

Contextual Info: fa tE ? \ ^^ ^ //P D 70 33 5 (V 35 Plus 16-Bit, Single-Chip CMOS Microcomputer . NEC Electronics Inc. Description The /xPD70335 (V35 Plus) is an enchanced version o f the (iPD70330 (V35 ) single-chip m icrocom puter providing higher speed (10 MHz) and greater functionality of onchip peripherals, including DMA, interrupt servicing, bus

new jn8

Abstract: DDR3 soDIMM pinout 204 pins
Contextual Info: Reference Manual DOC. REV. 10/17/2013 VL-EPM-35 Leopard Intel Dual Core Based Dual Board Computer with Dual Gigabit Ethernet, SATA, PC/104-Plus, Video, Audio, and SPX WWW.VERSALOGIC.COM 12100 SW Tualatin Road Tualatin, OR 97062-7341 (503) 747-2261 Fax (971) 224-4708

8130A

Abstract: ULN8130A
Contextual Info: ULN-8130A PRECISION SUPERVISORY SYSTEMS MONITOR ULN-8130A PRECISION SUPERVISORY SYSTEMS M O N ITO R Q uad Voltage and Line Monitor FEATURES • 10 V to 35 V Operation • Low Standby Current GROUND • Reference Trimmed to 1% • M onitors 4 Separate DC Levels

BA662

Abstract: sp501 SP501A
Contextual Info: SP501 SIGNAL PROCESSING EXCELLENCE flexiPORT Multi-Mode Serial Transceiver • Supports Industry Standard SoftwareSelectable Protocols: • RS232 V.28 • RS422A (V.11, X.27) • RS423A (V.10, X.26) • RS449 • RS485 • V.35 •MIL-STD-188C • MIL-STD-188-114A, Unbalanced

EPM1270

Abstract: F256 TQFP 256 h15 227 1 EPM1270G C9A10 EPM1270T144
Contextual Info: Dedicated Pin Information for the MAX II EPM1270 / EPM1270G Devices Version 1.5 Dedicated Pin IO/GCLK0 IO/GCLK1 IO/GCLK2 IO/GCLK3 IO/DEV_OE IO/DEV_CLRn TDI TMS TCK TDO GNDINT GNDIO 144-Pin TQFP 18 20 89 91 60 61 34 33 35 36 17, 54, 92, 128 10, 26, 47, 65, 83, 99, 115, 135

Contextual Info: FEATURES Dual 12-bit SAR ADC Simultaneous sampling Throughput rate: 5 MSPS per channel Specified for VDD of 2.5 V No conversion latency Power dissipation: 35 mW at 5 MSPS On-chip reference: 2.048 V ± 0.5% @ 25°C, 10 ppm/°C Dual conversion with read High speed serial interface: SPI -/QSPI -/MICROWIRE™-/

Contextual Info: 19-2173; Rev 1; 7/06 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs -40°C to +85°C 48 TQFP-EP* *EP = Exposed paddle. +Denotes lead-free package. 37 38 39 40 41 42 43 44 36 2 35 3 34 4 33 5 32 6 31 MAX1183 7 30 8 29 9

Contextual Info: 19-2173; Rev 1; 7/06 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs -40°C to +85°C 48 TQFP-EP* *EP = Exposed paddle. +Denotes lead-free package. 37 38 39 40 41 42 43 44 36 2 35 3 34 4 33 5 32 6 31 MAX1183 7 30 8 29 9

Contextual Info: 19-2173; Rev 1; 7/06 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs -40°C to +85°C 48 TQFP-EP* *EP = Exposed paddle. +Denotes lead-free package. 37 38 39 40 41 42 43 44 36 2 35 3 34 4 33 5 32 6 31 MAX1183 7 30 8 29 9

CM16022A

Abstract: 20pin lcd PLCC44 socket 3528 20pin 2pin male connector tantal 100UF 16V ATF16V8B-15PC LCD 16PIN Ceratech Atmel LCD 16x2
Contextual Info: EVB8051 V3.1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 LOCATION C1,C2 BC1-BC5,BC8,C8,C11 C3-C5,C6,C7 C13 C9,C10 R1,R2,R3,R4 R8,R15 R5 L1 D1, D2 D3 JP4,JP5 JP6,JP7 JP6,JP7 J1 P1 J3 J2 JP2 JP2 JP3 SW1

CXD2485AR

Contextual Info: CXD2485AR 1/3 IL08 TIMING GENERATOR WITH CCD ELECTRICAL IMAGE STABILIZER CONTROL VCC6 VEE4 VCC4 VCC3 VDD1 GND2 GND1 VCC5 GND3 VCC2 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 VEE 36 35 34 33 32 31 30

smd marking BA13

Abstract: smd marking G28 ad38 SMD qml-38535 marking ZZA SMD MARKING CODE P28 TR AK40 smd code AA5 smd marking CODE G28 MO-192-BAU-1
Contextual Info: REVISIONS LTR DESCRIPTION DATE APPROVED Y R -M O -D A REV SHEET 35 36 37 38 39 40 41 15 16 17 18 19 20 21 22 23 24 25 26 26 28 29 30 31 32 33 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 REV SHEET REV STATUS OF SHEETS REV SHEET PMIC N/A STANDARD MICROCIRCUIT DRAWING

Contextual Info: LZ95G824 1/3 IL22 * C-MOS GATE ARRAY LSI GND VDD (+5V) GND GND 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 GND VDD (+5V) 36 35 34 33 32 31 30 29 28 27 26 25 -TOP VIEW- (VDD = +5V) PIN I/O No.

FP-100B

Contextual Info: 1.3 Pin Arrangement FP-100B TFP-100B TFP-100G TOP VIEW NMI OSC1 OSC2 MD1 PH7/TONED/TMCI4 AVcc Vref P40/AN0 P41/AN1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Contextual Info: CXD1265R 1/3 IL08 TIMING PULSE GENERATOR FOR CCD CAMERA 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 —TOP VIEW— 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Contextual Info: CXD2460R-T4 1/3 IL08 TIMING GENERATOR FOR CCD IMAGE SENSOR 36 35 34 33 32 31 30 29 28 27 26 25 —TOP VIEW— 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 PIN NO. I/O SIGNAL PIN NO. I/O SIGNAL 1 2 3 4

LC867224A

Contextual Info: LC867224A-5J32 1/2 IL08 8-BIT MICROPROCESSOR 51 55 60 65 70 75 80 —TOP VIEW— 50 81 85 45 90 40 95 35 31 PIN NO. I/O SIGNAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O — I O — I

Contextual Info: Voltage Variable Absorptive Attenuator 35 dB, 0.5-2.0 GHz Functional Schematic 1,2,3 Features • • • • • • • AT-109 V3 Single Positive Voltage Control 0 to +5 Volts 35 dB Attenuation Range at 0.9 GHz ± 2 dB Linearity from BSL Low DC Power Consumption

Contextual Info: Silicon Bipolar MMIC Cascadable Amplifier MA4TD0385, MA4TD0386 V3.00 Case Style 85 Features ● ● ● ● ● ● GROUND Cascadable 50Ω Gain Block 3 dB Bandwidth: DC to 1.5 GHz 11.5 dB Typical Gain @ 1.0 GHz Unconditionally Stable k>1 Low Cost Plastic and SMT Packages

V3-2409S

Abstract: V3-0515S v3-0505s V3-0509S v3-0512s V3-2405S v3-1212s V3-2415S V3-1215S d0224
Contextual Info: V3-S/D01 02 Series MOTIEN TECHNOLOGY 2W Unregulated Dual Separate output Features T he V3 series is a family of cost effective 2W dual separate output DC-DC converters. These converters achieve low cost and ultraminiature SIP 7 pin or DIP 14 pin size. Devices are encapsulated using flame retardant resin. The models operate from input voltage of 5,