1.536MHZ Search Results

GSR-V

Abstract: DIP20 M5913 M5913B1
Contextual Info: M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS

DIP20

Abstract: M5913 M5913B1
Contextual Info: M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS

GSR-V

Abstract: Ringing Subscriber Line Interface Circuit NXP DIP20 M5913 M5913B1
Contextual Info: M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS

Contextual Info: /= T * 7 # . S G S -T H O M S O N M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER • SYN CHRO N O US C LO C K S ONLY ■ AT&T D3/D4 AND C C IT T CO M PATIBLE ■ TW O TIMING M ODES: FIX ED DATA R A TE MODE 1.536MHz, 1.544MHz, 2.048MHz V A R IA B LE DATA MODE: 64KHz - 4.096MHz

KM-59-13

Abstract: TS encoder 1SS150
Contextual Info: r= J ^ 7/, SG S -T H O M S O N KÆD [E] [i[L[l©Tr^ 2 R!lD©i M 5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER • SYNCHRONOUS CLOCKS ONLY ■ AT&T D3/D4 AND CCITT COMPATIBLE . TW O TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz

TP3094

Abstract: TP3094V
Contextual Info: TP3094 COMBO Quad PCM Codec/Filter General Description Features • Handles four voice channels • Complete Codec and Filter system including: The TP3094 is a monolithic PCM Codec and Filter device implemented using a digital signal processing architecture. It provides four voice

H1041

Abstract: TQFP64 package
Contextual Info: Product Brochure for INTC-Q 11/97 Intelligent Network Termination Controller PEB/PEF 8191 The Intelligent Network Termination Controller INTC-Q is a one-chip NT for the ISDN. The INTC-Q is used for Intelligent NTs, NT 1s and U- or S-terminals as well as terminal adaptors (TA). The INTC-Q provides the 2B1Q-U-interface

JESD65

Abstract: NJU26904 NJU26904VC2 24I2S
Contextual Info: NJU26904 デジタルオーディオディレイ • 概要 ■外形 NJU26904はデジタルオーディオ用のディレイ専用ICです。内部にメモリを持ち6 チャンネル音声信号の出力時間に遅延を与えることができます。

QFP48

Abstract: NJU26200 NJU26200FN2 NJU26200V NJU26201 NJU26249 SSOP44
Contextual Info: NJU26200 シリーズ NJU26200 シリーズハードウェア共通仕様書 概要 NJU26200 シリーズは24 ビット DSP コアのデジタル･オーディオ･ プロセッサです。この仕様書は、NJU26200 シリーズ ハードウェアの

tp3094

Abstract: TP3094V V44A
Contextual Info: TP3094 COMBO Quad PCM Codec/Filter General Description Features • Handles four voice channels • Complete Codec and Filter system including: The TP3094 is a monolithic PCM Codec and Filter device implemented using a digital signal processing architecture. It provides four voice

coil low pass subwoofer circuit diagram

Abstract: 0X501H
Contextual Info: April 12, 2012 Stereo Class D Spatial Array General Description Features The LM48903 is a stereo Class D amplifier that utilizes TI’s proprietary spatial sound processor to create an enhanced sound stage for portable multimedia devices. The Class D output stages feature National’s edge rate control ERC

Contextual Info: SIEMENS IS D N S u b s c rib e r A c c e s s C o n tro lle r fo r U pn-In te rfa c e T e rm in a ls S m a rtL in k -P PSB 2197 Preliminary Data 1 CMOS 1C Features • Cost/performance-optimized Upn-interface transceiver, compatible to PEB 2096 OCTAT-P and

STLC5411

Abstract: DIP28 PLCC44 ST5421 ST5451 STLC5411FN STLC5411P
Contextual Info: STLC5411 2B1Q U INTERFACE DEVICE GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS MEETS OR EXCEEDS ANSI U.S. AND ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE HCMOS3A SGS-THOMSON ADVANCED

Contextual Info: *4^, M icro L in e a r ML2020 Telephone Line Equalizer GENERAL DESCRIPTION FEATURES The ML2020 is a monolithic analog line equalizer for telephone applications. The ML2020 consists of a switched capacitor filter that realizes a family of frequency response

IDT821054

Abstract: IDT821054-XQ
Contextual Info: IDT821054 Programmable Quad PCM CODEC Preliminary Data Sheet, March 2001 Ver 1.0 File No. IDT821054DS(L)

Contextual Info: XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in

microcontroller based caller id by using 8051

Abstract: sound activated based lcd message display 8051 0038a 8088 memory interface SRAM ECHO canceller IC ED11 ED12 ED13 MX93002 MX93032
Contextual Info: MX93032 APPLICATION NOTE [M1 VERSION] 1.0 GENERAL DESCRIPTIONS echo cancellation and acoustical echo cancellation, etc. • The MX93032-M1 has built-in DSP mode and MCU mode. In DSP mode, users do not need external microprocessors and can effectively reduce the overall

v 12276

Abstract: KS8620 KS8620D KS8620N BCK 2501
Contextual Info: 1 Chip CODEC for Digital Answering phone KS8620 INTRODUCTION 16-DIP-300 The KS8620 consists of on-chip PCM encoders, decoders PCM CODECs and PCM line filter. This device provide all the functions required to interface a fullduplex voice telephone circuit, digital answering phone.

42750

Abstract: 6744A 157D
Contextual Info: WM8910 w Ultra Low Power DAC for Portable Audio Applications DESCRIPTION FEATURES The WM8910 is a high performance ultra-low power stereo DAC optimised for portable audio applications. • The device features stereo ground-referenced headphone amplifiers using the Wolfson ‘Class-W’ amplifier techniques

QFP48 package

Abstract: QFP48 NJU26201 NJU26249 SSOP44 NJU26200 NJU26200FR3 NJU26200V no17p
Contextual Info: NJU26200 Series NJU26200 Series Hardware Specification • General Description ■Package This document describes the NJU26200 Series common hardware specifications. This document is applied to the NJU26201 up to the NJU26249. The individual function is described in the each data sheet. Please refer to the

Contextual Info: EVALUATION KIT AVAILABLE MAX98091 Ultra-Low Power Stereo Audio Codec General Description The MAX98091 is a fully integrated audio codec whose high-performance, ultra-low power consumption and small footprint make it ideal for portable applications. The device features a highly flexible input scheme with

CD4046 tone decoder

Abstract: ST811 PLL CD4046 application CD4046 pll application note CD4046 vco rotary binary coder S3507 S35061 S-350-7
Contextual Info: MAM I S3506I/S35071/S3507AI Industrial Temperature — is t a n d a r d p r o d u c t s CMOS Single Chip ¡¿-Law/ A-Law Synchronous Combo Codecs With Filters Features February 1993 • Encoder has Dual-Speed Auto-Zero Loop for Fast Acquisition on Power-up

advantages of digital pulse counter

Abstract: synthesizer 144mhz XC4000 XC4003 XC4085XL Direct Digital Frequency Synthesizer
Contextual Info: FPGA APPLICATIONS Frequency Synthesis FPGAs can simplify frequency synthesis without adding complexity, quite often improving performance. Here are some useful techniques. by Austin Lesea, Principal Engineer, Xilinx, austin.lesea@xilinx.com F requency synthesis is often used in digital designs, and

Contextual Info: FINAL a Am79C30A/32A Advanced Micro Devices Digital Subscriber Controller DSC™ Circuit DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T-lnterface Transceiv­ er, D-Channel LAPD Processor, Audio Proces­ sor (DSC device only), and IOM-2 Interface in a