0K11F Search Results

80L188EB

Contextual Info: Â W Â K K g i 0K11F@ 1^IM ]Ä?0 K1 in te i 28F200BX-TL/BL, 28F002BX-TL/BL 2 MBIT 128K x 16,256K x 8 LOW POWER BOOT BLOCK FLASH MEMORY FAMILY • Low Voltage Operation for Very Low Power Portable Applications — VCC = 3.3V ±0.3V ■ x8/x16 Input/Output Architecture

Intel Microprocessor 240440

Abstract: 82360SL intel 82360SL
Contextual Info: in te i November 1992 Intel486 SL Microprocessor SuperSet Data Book Order Number: 241325-001 2-1 Intel486™ SL Microprocessor SuperSet CONTENTS CONTENTS page page 1.0 INTRODUCTION . 2-6 3.0 82360SL I/O SPECIFICATIONS . . . . 2-79

82360sl

Abstract: CT674 sd4093 ca10 switch a007 LT1667 socket lga 1156 pinout 451 80 N02 LT1651 LT1665 u1620
Contextual Info: in te i lntel386 SL MICROPROCESSOR SuperSet Highly-Integrated Static Intel386™ SL Microprocessor Complete ISA Peripheral Subsystem System-Wide Power Management — H ig h -S p ee d P erip h eral In te rfa c e Bus P l-B u s S u p p o rt — N e w id e a P o rt In te rfa c e fo r H a rd w a re

Contextual Info: inteT O M F @ fô !M Â T D N ] 82560 HOST INTERFACE AND MEMORY CONTROLLER Host Interface to the IBM PC/XT/AT and P S / 2TM Buses for 82590, 82592 Allows 16- and 8-Bit Data Transfers Supports Local Static RAM — Up to 16 Kilobytes — Programmable Access Time

80C186 USER MANUAL

Contextual Info: • . ? m m Ü07300S 3 EU ITL2 . ^ INTEL CORP MEMORY/PLI / 82593 ' — CSMA/CD CORE LAN CONTROLLER ■ Supports Industry Standard LANs — IEEE 10BASE5 (Ethernet*) — IEEE 10BASE2 (Cheapernet) — IEEE 10BASE-T (TPE) ■ Simple, High-Performance Control and

82374EB/82374SB

Contextual Info: Ä I W Ä 1 OMIF ISBM!rD@M in tei 82374EB EISA SYSTEM COMPONENT ESC Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/

82485

Contextual Info: Â M © 1 DGsOF@K[MÄ¥D Kl J n te l DEC 05 82485 SECOND LEVEL CACHE CONTROLLER FOR THE Ì486TM MICROPROCESSOR High Performance — Zero Wait State Access on Cache Hit — One Clock Bursting — Two-Way Set Associative — Write Protect Attribute Per Tag

Contextual Info: in t e i MILITARY i486 MICROPROCESSOR Binary Compatible with Large Software Base -M S -D O S *, O S /2*, Windows — U NIX* System V/386 — iRMX , iRM KTM Kernels Easy To Use — Built-In Self Test — Hardware Debugging Support — Intel Software Support