0FIC13 Search Results

Contextual Info: H ig h P e r f o r m a n c e 64K X 32 C M O S SRA M n II A S7C 36432 6 4 K X 3 2 Synchronous burst SRAM Preliminary information • O r g a n iz a tio n : 6 5 , 5 3 6 w o r d s x 3 2 b its • A s y n c h r o n o u s o u t p u t e n a b le c o n tr o l • F u lly s y n c h r o n o u s p ip e lin e d o p e r a tio n

74AC11648

Abstract: A0237
Contextual Info: TEXAS INSTR 31E LOGIC D • 3^1723 □0fic130t> b ■ T I I3 54AC11648, 74AC11648 OCTAL BUS TRANSCEIVERS AND REGISTERS -T ' 3 2 .-3 1 • Independent Registers A and B Buses • Multiplexed Real-Time and Stored Data • Inverting Data Paths • Flow-Through Architecture to Optimize