08AUG20 Search Results

390261-2

Abstract: logo 230 r
Contextual Info: 4 T H IS D R A W IN G IS U N P U B L IS H E D . R ELEASED FO R P U B L IC A T IO N ALL C O P Y R IG H T BY TYCO 2 3 E L E C T R O N IC S R IG H T S - , - LOC RESERVED. AD C O R P O R A T IO N . D IS T REVISIO N S D E S C R IP T IO N 08AUG2007 ECO—0 7 —0 1 7 3 6 3

Contextual Info: 4 RELEASED FOR PUBLICATION THIS DRAWING IS UNPUBLISHED. C COPYRIGHT 20 2 3 1 20 LOC - ALL RIGHTS RESERVED. BY - -A- REVISIONS DIST - P LTR A A1 -A- DESCRIPTION DATE DWN APVD REVISED PER ECR-12-002666 08AUG2012 RS MM REVISED PER ECR-14-000133 22JAN2014 YR OL

Contextual Info: T H IS D R A W IN G IS U N P U B L IS H E D . RELEASED FO R ALL C O P Y R IG H T By P U B L IC A T IO N R IG H TS REVISIO N S RESERVED. - LTR D E S C R IP T IO N DATE 1 JM E C O —1 3 —0 1 2 6 3 6 5 .7 0 DWN 08AUG20 3 A PVD TE REF 1278637-1 1. TOOL NOT INTENDED TO

Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. C COPYRIGHT 20 RELEASED FOR PUBLICATION TE Connectivity 6 5 4 3 2 20 LOC GP ALL RIGHTS RESERVED. ORGANIZER CONTACTS 1 MATERIAL: 2 FINISH: D 1 REVISIONS DIST 00 P LTR DESCRIPTION DATE DWN APVD D RELEASED PER ECO-12-014574 08AUG2012

Contextual Info: 2 THIS DRAWING IS UNPUBLISHED. C O P Y RI G HT 20 BY RELEASED TYCO ELECTRONICS CORPORATION. ALL FOR PUBLICATION R|3 H T $ LOC GP RESERVED. REV I S I O N S D I ST 00 LTR DE SC R I P T I O N D WN DATE NEW R E L E A S E 08AUG2007 APVD PD RG P A R T N U M B P R C H A N G P S A N D OR D P S I G N C H A N G P G A P P P C T I N G

ENE3127B

Abstract: NDK America ndk TCXO STCD1020 STCD1020RDG6E STCD1030 STCD1040 STCD1040RDM6F TDFN12
Contextual Info: STCD1020, STCD1030, STCD1040 Multichannel clock distribution circuit Features • 2, 3 or 4 outputs buffered clock distribution ■ Single-ended sine wave or square wave clock input and output ■ Individual clock enable for each output ■ Lower fan-out on clock source

JESD97

Abstract: STD100NH02L STD100NH02L-1 STD100NH02LT4
Contextual Info: STD100NH02L STD100NH02L-1 N-channel 24V - 0.0042Ω - 60A - DPAK - IPAK STripFET II Power MOSFET General features Type VDSSS RDS on ID STD100NH02L STD100NH02L-1 24V 24V <0.0048Ω <0.0048Ω 60A(1) 60A(1) 3 3 2 1 1. Value limited by wire bonding • RDS(on) * Qg industry’s benchmark

360N4F6

Contextual Info: STI360N4F6, STP360N4F6 N-channel 40 V, 120 A STripFET VI DeepGATE™ Power MOSFET in I²PAK and TO-220 packages Datasheet − preliminary data Features Order codes STI360N4F6 STP360N4F6 VDSS RDS on max ID 40 V < 1.8 mΩ 120 A(1) TAB TAB 1. Current limited by package

Contextual Info: 100355 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable En inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or

27014QS

Abstract: 5962R9059001SZA
Contextual Info: 54AC05 Hex Inverter with Open Drain Outputs General Description Features The ’AC05 contains six inverters. n Outputs sink 24 mA n Open drain for wired NOR function n Standard Microcircuit Drawing SMD 5962-9059001 Logic Symbol IEEE/IEC DS100981-1 Connection Diagrams

SE8012L

Abstract: se8012
Contextual Info: SE8012L 0.5 dB LSB 6-bit Attenuator with Digital Control, 0.5 – 6.0 GHz Preliminary Datasheet Applications ‰ ‰ ‰ ‰ Product Description The SE8012L is a silicon based 6-bit digital attenuator with parallel logic control. Cellular/3G/4G Infrastructure

High Level Mixer

Abstract: 115 ssb lob
Contextual Info: SE8002L Down-Converter Mixer Preliminary Datasheet Applications ‰ ‰ ‰ ‰ Product Description 3G/4G base station transceivers: CDMA, UMTS/WCDMA, LTE Point to Point Microwave Radio Links ISM band transceivers Fixed Broadband Wireless Access Features: ƒ ƒ

EEPROM 28128

Abstract: HC16201-a HC16201 diode LT 42 PR 3002 dk4000 design desktop motherboard tutorial rm10j1 tn lcd display module for clock c1318 AN054 JTAG Information
Contextual Info: DK4000-ST10 USER MANUAL Development Kit for PSD4000 and ST10 CONTENTS • A COUPLE OF DEFINITIONS – IAP – ISP ■ DETAILED DESCRIPTIONS ■ OTHER BOARD FEATURES – Step-By-Step Instructions for ISP Programming – Step-By-Step Instructions for IAP Programming

SAC405

Abstract: GRM155R71C104KA01 SARA-G340 SARA-G300 SARA-U260
Contextual Info: SARA-G3 and SARA-U2 series GSM/GPRS and GSM/EGPRS/HSPA Cellular Modules System Integration Manual Abstract This document describes the features and the system integration of the SARA-G3 series GSM/GPRS cellular modules and the SARA-U2 GSM/EGPRS/HSPA cellular modules.

Contextual Info: M68AF511AL 4 Mbit 512K x8 , 5V Asynchronous SRAM FEATURES SUMMARY • SUPPLY VOLTAGE: 4.5 to 5.5V ■ 512K x 8 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55ns ■ LOW STANDBY CURRENT ■ LOW VCC DATA RETENTION: 2V ■ TRI-STATE COMMON I/O

Contextual Info: L9733 Octal self configuring low/high side driver Features • Eight independently self configuring low/high drivers ■ Supply voltage from 4.5V to 5.5V ■ RON max =0.7Ω @ Tj = 25°C, RON(max)=1.2Ω @Tj = 125°C ■ Minimum current limit of each output 1A

Contextual Info: M48T201Y M48T201V 5.0 or 3.3V TIMEKEEPER supervisor Features • Converts low power SRAM into NVRAMs ■ Year 2000 compliant ■ Battery low flag ■ Integrated real time clock, power-fail control circuit, battery and crystal ■ Watchdog timer ■ Choice of write protect voltages

IN-67

Contextual Info: L9733 Octal self configuring low/high side driver Features • Eight independently self configuring low/high drivers ■ Supply voltage from 4.5 V to 5.5 V ■ RON max = 0.7 Ω @ Tj = 25 °C, RON(max) = 1.2 Ω @Tj = 125 °C ■ Minimum current limit of each output 1 A

JESD97

Abstract: STC5NF30V MOSFET MARKING ST
Contextual Info: STC5NF30V N-channel 30V - 0.027Ω - 5A - TSSOP8 2.7V-drive STripFET II Power MOSFET General features Type VDSS RDS on ID STC5NF30V 30V < 0.031 Ω ( @ 4.5 V ) < 0.035 Ω ( @ 2.7 V ) 5A • Ultra low threshold gate drive (2.7V) ■ Standard outline for easy automated surface

D15NF10

Abstract: STD15NF10 75A12 JESD97 STD15NF10T4
Contextual Info: STD15NF10 N-channel 100 V, 0.060 Ω, 23 A, DPAK low gate charge STripFET II Power MOSFET Features Type VDSSS RDS on max ID STD15NF10 100 V < 0.065 Ω 23 A 3 1 • Exceptional dv/dt capability ■ 100% avalanche tested ■ Application oriented characterization

Contextual Info: STD110NH02L N-channel 24V - 0.0044Ω - 80A - DPAK STripFET III Power MOSFET General features Type VDSSS RDS on ID STD110NH02L 24V <0.0048Ω 80A(1) 3 1. Value limited by wire bonding • RDS(on) * Qg industry’s benchmark ■ Conduction losses reduced

Contextual Info: Preliminary Data Sheet Part Number 855927 169 MHz SAW Filter Features • • • • • • For UMTS basestation applications Usable bandwidth 4 MHz Low loss Single-ended to balanced operation Ceramic Surface Mount Package SMP Package Pin Configuration

Contextual Info: 2 THIS DRAWI NG IS UNPUBLISHED. C O P Y R I G H T 20 R E L E A S E D FOR P U B L I C A T I O N BY TYCO E L E C T R O N I C S C O R P O R A T I O N . A L L 20 LOC ES R 1G H T S R E S E RV E D. R E V 1S I O N S DIST 00 P LTR D D2 D3 D4 MATERIAL: T HERMO PLASTIC,

Contextual Info: 4 RELEASED FOR PUBLICATION 30.SEP. FREI FUER VEROEFFENTLICHUNG ALL RIGHTS RESERVED. ALLE INTERNATIONALEN RECHTE VORBEHALTEN. THIS DRAWING IS UNPUBLISHED. VERTRAULICHE UNVEROEFFENTLICHTE ZEICHNUNG C COPYRIGHT TE Connectivity 2010 2 3 2010 MATED WITH: PASSEND ZU: