07JUN07 Search Results

SOIC-24

Abstract: CAT9554 CAT9555 CAT9555WI CAT9555WI-T1 CAT9555YI MO-220 MS-013
Contextual Info: CAT9555 16-bit I²C and SMBus I/O Port with Interrupt FEATURES DESCRIPTION „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ The CAT9555 is a CMOS device that provides 16-bit parallel input/output port expansion for I²C and SMBus compatible applications. These I/O expanders provide

CAT9554

Abstract: CAT9555 CAT9555WI CAT9555WI-T1 CAT9555YI MO-220 MS-013
Contextual Info: CAT9555 16-bit I²C and SMBus I/O Port with Interrupt FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DESCRIPTION 1 400kHz I²C bus compatible 2.3V to 5.5V operation Low stand-by current 5V tolerant I/Os 16 I/O pins that default to inputs at power-up

CAT9554

Abstract: CAT9555 MO-220 MS-013
Contextual Info: CAT9555 16-bit I²C and SMBus I/O Port with Interrupt FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DESCRIPTION 400kHz I²C bus compatible 2.3V to 5.5V operation Low stand-by current 5V tolerant I/Os 16 I/O pins that default to inputs at power-up High drive capability

411-78008

Abstract: tyco 411-78008 108-5793
Contextual Info: 4 TH 1 S DRAW 1 NG C 1S 3 U N P U B L 1S H E D . COPYRIGHT RELEASED BY TYCO ELECTRONICS POR CORPORATION. PUBLICATIO N ALL R 1^ H T S REV I S IONS LOC RESERVED. DESCR I PTI ON LTR RELEASED .7 REF ADD 01 FJ00-2 "-2" SLIT 0I I OOCTOI EC R -0 5 000427 09MAR2005

10uF-TC3216

Abstract: fpga256 dm9161aep LTC1765 Omron SPEED sensor 12v m16 free circuit diagram ad1981b mother board g31 FPGA208 XC32P AT91CAP-MEM18
Contextual Info: AT91CAP7X-DK Development Kit . User Guide 8506A–CAP–2/08 Table of Contents Section 1 1.1 Scope. 1-1

MTA-156

Contextual Info: 4 T H IS D R AW IN G IS U N P U B L IS H E D . C O PYRIG H T 2 3 R E LE A S E D EOR P U B LIC A T IO N BY TYCO ELEC TR O N IC S CO RPO RATIO N . -, - LOC A LL R IG H T S R E S E R V E D . R E V IS IO N S D IS T 00 D E S C R IP T IO N D ECO —0 7 —0 1 2 8 5 9

J34-J35

Abstract: B 342 Dc ml2020 panasonic battery capasitor QFN40P500X500X80-40N LP3971 ml2020 HEADER 8 PIN OSC-SMT DVM panel
Contextual Info: 1.0 Design Description The LP3971 Smart Power Board provides a complete, multirail solution for FPGAs, Microprocessors, or any other systems requiring multiple voltages, special power sequencing, and boot management. This solution utilizes the National Semiconductor LP3971 Power Management Unit and an 8 bit

CAT9554

Abstract: CAT9555 CAT9555WI CAT9555WI-T1 CAT9555YI MO-220 MS-013
Contextual Info: CAT9555 16-bit I²C and SMBus I/O Port with Interrupt FEATURES DESCRIPTION „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ The CAT9555 is a CMOS device that provides 16-bit parallel input/output port expansion for I²C and SMBus compatible applications. These I/O expanders provide

114-13120

Contextual Info: 2 THIS C DRAWING IS UNPUBLISHED. C O P Y R I G H T 20 BY - RELEASED ALL FOR PUBLICATION RIGHTS 20 LOC RESERVED. GP DIST REVISIONS 00 LTR DESCRIPTION REVISED B I PER DATE ECO-1 1-0 048 35 DWN I IMARZO I I RK APVD HMR I- 9 . 0 0 ±0 . 20 A MATER IAL: CAGE ASSEMBLY - 0.25mm THICK

K 3566

Abstract: t7 aeg
Contextual Info: 4 T H IS D R A W IN G IS 3 U N P U B L IS H E D . R ELEASED FO R P U B L IC A T IO N ALL C O P Y R IG H T B Y TYCO E L E C T R O N IC S R IG H T S - 2 , - LOC RESERVED. R E V IS IO N S D IS T 00 C O R P O R A T IO N . D E S C R IP T IO N D "d T ECO —0 7 —0 1 2 8 5 9

cd 5151

Abstract: MTA-156
Contextual Info: 4 T H IS D R AW IN G IS U N P U B L IS H E D . C O PYRIG H T 2 3 -, R E LE A S E D EOR P U B LIC A T IO N BY TYCO ELEC TR O N IC S CO RPO RATIO N . - LOC A LL R IG H T S R E S E R V E D . R E V IS IO N S D IS T 00 D E S C R IP T IO N D ECO —0 7 —0 1 2 8 5 9

Contextual Info: Crystek Corporation AVAILABLE PERFORMANCE SPECIFICATION Lower Frequency: Upper Frequency: Tuning Voltage: Supply Voltage: Output Power: Supply Current: Harmonic Suppression, 2nd: Pushing: Pulling, all Phases: Tuning Sensitivity: Phase Noise @ 10kHz offset:

dm9161aep board

Contextual Info: AT91CAP9A-DK Development Kit . User Guide 6321B–CAP–02-Jul-07 1-2 6321B–CAP–02-Jul-07 AT91CAP9A-DK Development Kit User Guide Table of Contents

Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. C COPYRIGHT 20 RELEASED FOR PUBLICATION BY - 6 5 4 3 2 20 LOC GP ALL RIGHTS RESERVED. 9.00 CAGE ASSEMBLY 0.20 1 REVISIONS DIST 00 P LTR DESCRIPTION DATE DWN APVD C REVISED PER ECO-11-024172 07DEC2011 TX AC C1 REVISED PER ECO-13-014018