0578J Search Results

Contextual Info: PRELIMINARY in te l 28F002BC 2-MBIT 256K X 8 BOOT BLOCK FLASH MEMORY High Performance Read — 80/120 ns Max Access Time 40 ns Max. Output Enable Time Low Power Consumption — 20 mA Typical Read Current x8-Only Input/Output Architecture — Space-Constrained 8-bit

ICS93732

Abstract: MO-150
Contextual Info: ICS93732 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz DDR 533

Contextual Info: 28F002BC 2-MBIT 256K X 8 BOOT BLOCK FLASH MEMORY • High Perform ance Read — 80/120 ns Max. Access Time 40 ns Max. Output Enable Time ■ Extended Cycling Capability — 100,000 Block Erase Cycles ■ Automated Byte W rite and Block Erase ■ Low Power Consumption

Contextual Info: ICS93732 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz DDR 533