0504B9 Search Results

TMP8237

Contextual Info: T O S H IB A TMP82C37A MULTIMODE DMA CONTROLLER TMP82C37AP-5/TMP82C37AM-5/TMP82C37AT-5 1. GENERAL DESCRIPTION T h e T M P 8 2 C 3 7 A P -5 /A M -5 /A T -5 h e r e in a f t e r r e f e r r e d to a s T M P 8 2 C 3 7 A is a m u ltim o d e d ire c t m e m o ry access (DM A) c o n tro lle r.

p82c59a

Abstract: P82C59 icw1
Contextual Info: T O S H IB A TMP82C59A TOSHIBA MOS TYPE DEGITAL INTEGRATED CIRCUIT Silicon Monolithic CMOS Silicon Gate TMP82C59AP-2/TMP82C59AM-2 PRO GRAM M ABLE INTERRUPT CONTROLLER 1. GENERAL DESCRIPTION TM P82C59AP-2/AM -2 h erein a fter referred to as TM P82C59A is a program m able

P8255

Abstract: P8255A P8255AP-5
Contextual Info: TOSHIBA TMP8255A PROGRAM M ABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES The TMP8255A hereinafter referred to as PPI is a high Speed program m able input/output interface with three 8 -bit I/O ports. 24 I/O ports are divided into two

Contextual Info: TOSHIBA TMP82C55A CMOS PROGRAM M ABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 1. GENERAL DESCRIPTION AND FEATURES T h e T M P 82C 55A h e r e in a f t e r r e f e r re d to a s P P I is a CM O S h ig h S peed program m able in p u t/o u tp u t interface w ith th ree 8 -b it I/O ports. 24 I/O P o rts are divided

TC74HC373P

Abstract: tr-5-t ssop40 TMP8237 TMP82C37A TMP82C37AM-5 TMP82C37AP-5 TMP82C37AT-5 TMP8237AP MPU85-207
Contextual Info: TO SH IBA TMP82C37A MULTIMODE DMA CONTROLLER TMP82C37AP-5/TMP82C37AM-5/TMP82C37AT-5 1. GENERAL DESCRIPTION The TM P82C37AP-5/AM -5/AT-5 h e re in a fte r referred to as TM P82C37A is a m ultim ode direct memory access (DMA) controller. The TM P82C37A im proves the

8156p

Abstract: TMP8156P tmp8155p tmp8155 TMP8155P-2 TMP8156P-2 8155 addressing mode TMP8085 MPU85
Contextual Info: TOSHIBA TMP8155/8156 TMP8155P-2/TMP8156P-2 256 BYTE STATIC RAM WITH I/O PORTS AND TIMER 1. GENERAL DESCRIPTION The T M P 8155/8156P -2 are RAM including I/O ports and counter/tim er on one chip for u sing in the T L C S -85A m icrocom puter system . The RAM portion is designed w ith 2K

TMP8237

Contextual Info: TOSHIBA TMP8237A MULTIMODE DM A CONTROLLER TMP8237AP-5 1. GENERAL DESCRIPTION The TM P8237AP-5 hereinafter referred to as TMP8237A is a m ultim ode direct m em ory access (DMA) controller. The TM P8237A improves the system function by directly transferrin g inform ation between the system memory and external devices.

Contextual Info: TOSHIBA TMP82C37A M U LT IM O D E D M A CONTROLLER TMP82C37AP-5/TMP82C37AM-5/TMP82C37AT-5 1. G EN ER A L DESCRIPTION The TMP82C37AP-5/AM-5/AT-5 hereinafter referred to as TMP82C37A is a multimode direct memory access (DMA) controller. The TMP82C37A improves the