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    SIMECH SPT00139C

    Wire: coiled; 3x0.35mm2; unshielded; PUR; black; 300V; 1m; 4m
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    TME SPT00139C 7 1
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    Diotec Semiconductor AG LDP01-39CAYD2R-AQ

    Diode: TVS; 5kW; 36.7÷42.2V; 94A; bidirectional; D2PAK; reel,tape
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    TME LDP01-39CAYD2R-AQ 1
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    Mouser Electronics LDP01-39CAYD2R-AQ
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    Newark LDP01-39CAYD2R-AQ Cut Tape 1
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    Diotec Semiconductor AG LDP01-39CAYD2-AQ

    Diode: TVS; 5kW; 36.7÷42.2V; 94A; bidirectional; D2PAK; tube
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    TME LDP01-39CAYD2-AQ 1
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    Mouser Electronics LDP01-39CAYD2-AQ
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    Newark LDP01-39CAYD2-AQ Bulk 1
    • 1 $2.51
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    ABLIC Inc. S-80139CNMC-JKYT2G

    - Tape and Reel (Alt: S-80139CNMC-JKYT2G)
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    Avnet Americas S-80139CNMC-JKYT2G Tape & Reel 16 Weeks 3,000
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    Mouser Electronics S-80139CNMC-JKYT2G
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    ABLIC Inc. S-80139CNPF-JKYTFU

    - Tape and Reel (Alt: S-80139CNPF-JKYTFU)
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    Avnet Americas S-80139CNPF-JKYTFU Tape & Reel 16 Weeks 5,000
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    0139C Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    MG139A

    Abstract: MG139C MS139A MS139C M0139
    Contextual Info: MS139A/C MG139A/C M0139A/C 0.39" SINGLE DIGIT NUMERIC DISPLAYS SEVEN SEGMENT NUMERIC DISPLAY High Performance GaP, GaAsP Dice 0.39 inch Character Height High Contrast Wide Viewing Angle Common Anode - MS139A, MG139A, M 0139A Common Cathode - MS139C, MG139C, M 0139C


    OCR Scan
    ms139a/cmg139a/cm0139a/cms139a+7mg139am0139ams139cmg139cm0139cms139m0139 PDF

    PLSI 1016-60LJ

    Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
    Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density


    Original
    1016e1032e20ters48-pin+11304-pinplsi 1016-60ljpal 007 pioneerpal16r8 programming algorithmpal 008 pioneerlattice 1016-60ljisp engineering kit - model 100plsi-2064-80ljgal16v8 programmer schematicgal programming guideisplsi 2064-80lt PDF

    isp1016ea

    Abstract: 0139C ISP1016E 1016E 1016EA lattice isp1016ea 1016ea100lt44 TMS3630
    Contextual Info: ispLSI 1016EA In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    1016ea1016e0212/1016ea1016ea-200lj44+844-pin1016ea-200lt44isp1016ea0139cisp1016elattice isp1016ea1016ea100lt44tms3630 PDF

    lattice isp1016ea

    Abstract: ispMACH 4A5 1016E 1016EA
    Contextual Info: ispLSI 1016EA In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    1016ea1016e44-pin1016ea-125lt44+41016ea-100lj441016ea-100lt44lattice isp1016eaispmach 4a5 PDF

    1016E

    Abstract: IN2129
    Contextual Info: ispLSI 1016E In-System Programmable High Density PLD Features Functional Block Diagram B7 Output Routing Pool A0 • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs


    Original
    1016e0212/1016e1016e-125lj44-pin+41016e-125lt441016e-100lj1016e-100lt44in2129 PDF

    1016E

    Abstract: 1016E-80LJ PLSI 1016E-80LT44 isplsi device layout
    Contextual Info: ® ispLSI and pLSI 1016E High-Density Programmable Logic • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable


    Original
    1016e1016e-80ljplsi 1016e-80lt44isplsi device layout PDF

    isp1016ea

    Abstract: 0139C ISP1016E 1016E 1016EA
    Contextual Info: ispLSI 1016EA In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    1016ea1016e0212/1016ea1016ea-200lj44+544-pin1016ea-200lt44isp1016ea0139cisp1016e PDF

    1016E

    Abstract: 1016E-100LJ 1016E-80LJ lattice 1016E speed performance of Lattice - PLSI Architecture
    Contextual Info: ispLSI and pLSI 1016E ® High-Density Programmable Logic • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable


    Original
    1016e1016e-100lj1016e-80ljlattice 1016e+1speed performance of lattice - plsi architecture PDF

    lattice isp1016ea

    Abstract: isp1016e lattice 1016E isp1016ea
    Contextual Info: ispLSI 1016EA In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    1016ea1016e0212/1016ea1016ea-200lj44+91016ea-200lt441016ea-125lj441016ea-125lt441016ea-100lj441016ea-100lt44lattice isp1016eaisp1016elattice 1016eisp1016ea PDF

    1016E

    Abstract: 0123A 1016e80lt44i
    Contextual Info: ispLSI 1016E In-System Programmable High Density PLD Features B7 A2 Logic A3 Array B5 D Q D Q GLB B4 B3 A4 D Q B2 A5 B1 A6 Global Routing Pool GRP EW A7 • IN-SYSTEM PROGRAMMABLE — In-System Programmable (ISP ) 5V Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality


    Original
    1016e0212/1016e1016e-125lj44-pin+51016e-125lt441016e-100lj1016e-100lt440123a1016e80lt44i PDF

    1016e80lt44i

    Abstract: 1016E 1016E-100
    Contextual Info: ispLSI 1016E In-System Programmable High Density PLD Features Functional Block Diagram B7 Output Routing Pool A0 • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs


    Original
    1016e0212/1016e1016e-125lj44-pin+51016e-125lt441016e-100lj1016e-100lt441016e80lt44i1016e-100 PDF

    1016E

    Contextual Info: ispLSI and pLSI 1016E ® High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    1016e PDF

    ISP1016E

    Abstract: 1016EA ISP1016EA 1016E Lattice isplsi 1016EA
    Contextual Info: ispLSI 1016EA In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    1016ea1016e0212/1016ea1016ea-200lj44+544-pin1016ea-200lt44isp1016eisp1016ealattice isplsi 1016ea PDF

    1016E

    Abstract: 1016E-80LJ
    Contextual Info: ispLSI and pLSI 1016E ® High-Density Programmable Logic Features Functional Block Diagram B7 Output Routing Pool A0 • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs


    Original
    1016e1016e-100lt441016e-80lj44-pin+11016e-80lt44 PDF

    100ltn44

    Abstract: 1016E ISPLSI 1016E-100LTN44
    Contextual Info: LeadFree Package Options Available! ispLSI 1016E In-System Programmable High Density PLD Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY


    Original
    1016e0139c1-isp1016e-100ltn4444-pin+51016e-80ljn1016e-80ltn441016e-80ljni100ltn44isplsi 1016e-100ltn44 PDF