007L4 Search Results

50HZ oscillator sinus vco

Abstract: 7b45 HP611 HCSA SAA7110 update MS24 SAA7110 SAA7197 TDA9150 CLL323
Contextual Info: Preliminary specification Philips Semiconductors SAA7110 One Chip Frontend 1 OFC1 Digital multistandard colour decoder with 2 A /D converters The YUV bus supports a data rate o f (780 x fh) for 60 Hz 12.2727MHz (NTSC) (944 x for 50 Hz 14.75MHz (PAL/SECAM)

Contextual Info: / T T SG S-THOM SO N *7 .t. ö!!i!D»i[LII gTl(MD(g§ TS75C32 V . 3 2 , V . 2 2 b is , V . 2 2 , V . 2 3 , V . 2 1 , B E LL 21 2A , B E LL 103 M O D E M C H IP S E T ADVANCE DATA • CCITT V.32, V22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM

brq ti

Abstract: BRQ TI 7C
Contextual Info: D National November 1995 Semiconductor </> co 00 •Nl cn DS3875 Futurebus+ Arbitration Controller General Description The DS3875 Futurebus+ Arbitration Controller is a member of National Semiconductor’s Futurebus+ chip set designed specifically for the IEEE 896.1 Futurebus+ standard. The

tsl usc1

Abstract: HD7x BL342
Contextual Info: S G S -T H O M S O N TS75C96 V.32, V.29, V.27ter, V.22bis, V.22, V.23, BELL 212A, BELL 103 MODEM CHIP SET ADVANCE DATA CCITT V.32, V.22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET CCITT V.29, V.27ter FOR FAX APPLICA­ TIONS INTEGRATED IMPLEMENTATION ON THREE

28F400BX-B

Abstract: 28F400BX-T 28F004BX-B 28F004BX-T intel PLD PA28F400BX
Contextual Info: INTEL CORP HENORY/PLD/ SbE D 4fl5bl7L, 007fc.44D 0 2 e! • i ITL2 D K lF O l^ lîü l T rO O M in te l 28F400BX-T/B, 28F004BX-T/B 4 MBIT (256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY Very High-Performance Read — 60/80 ns Maximum Access Time — 30/40 ns Maximum Output Enable

TS902

Abstract: K7-T
Contextual Info: SCS-THOMSON TS902 " ” " ~ ~ ~ ![L I ra § K D 0 © § INPUT/OUTPUT RAIL TO RAIL DUAL CMOS OPERATIONAL AMPLIFIER WITH STANDBY POSITION) • RAIL TO RAIL INPUT AND OUTPUT VOLTAGE RANGES ■ STANDBY POSITION: REDUCED CON­ SUMPTION (1|uA) AND HIGH IMPEDANCE