00500EL Search Results

WA-LS367

Abstract: LS367 WP90353
Contextual Info: A T & T MELEC BE I C 00500EL. QQOGESO 7 • 8 2D 0 0 2 5 0 DT - H 3 - Ï S D WA-LS367, WP90353 List 2 Hex 3-State Buffer with Separate 2-Bit and 4-Bit Sections The LS367 is a bipolar, NPN, sealed-junction, silicon integrated circuit. It is manufactured in low-power

Contextual Info: BE T & T MELEC I C 00500EL. QGOGESO 7 • 82D 0 0 2 5 0 DT - H 3 - Ï S D WA-LS367, WP90353 List 2 Hex 3-State Buffer with Separate 2-Bit and 4-Bit Sections The LS367 is a bipolar, NPN, sealed-junction, silicon integrated circuit. It is manufactured in low-power

sine wave generator using ic 555

Abstract: PIN DIAGRAM of LM 324 pwm pure sine wave generator Internal diagram of ic 7495 pwm 555 driver application ATTL7590AAE JE22 L7590 pin diagram of ic 7495 HP3311A
Contextual Info: Advance Data Sheet March 1997 m icroelectronics group Lucent Technologies Bell Labs Innovations L7590 Telephone Ringing Driver Description Features Applies a battery-backed, single-ended, sinusoidal ringing signal to the telephone loop The L7590 Telephone Ringing Driver produces a lowfrequency sinusoidal ringing signal for analog tele­

DSP1610 Simulator

Abstract: PDA30 LP 1610 DSP16A PDA30 SPEED DSP1610 a1T35 MXM pin assignment DB10 DSP16
Contextual Info: g ^ A Data Sheet May 1995 T & T Microelectronics DSP1610 Signal Coding Digital Signal Processor 1 Features 2 Description • 25 ns or 33 ns instruction cycle The DSP1610 Signal Coding DSP is a 16-bit, high­ speed, programmable integrated circuit fabricated in

DSP16A

Abstract: cis linear 2400 HSM144DD HSM144LD HSM144PD T7525 Rockwell V.17 Training EQUALIZER ERROR FILTER SCRAMBLE SAMPLE marking ma4 wedsp16a
Contextual Info: A T & T MELCC I C btE II • DDSÜDSb DDPTtbl 1R8 « A T T ä ATsT June 3" 1993 ^ M ic r o e le c tr o n ic s AT&T HSM144xD Data Pump Chip Sets (14,400 bits/s Data/FAX, ROM Code MA) Introduction Features The AT&T HSM144xD Data Pump Chip Sets allow modem designers to build high-speed, fully-featured

Contextual Info: Preliminary Data Sheet April 1995 A TnT iË Ë É i 1 Microelectronics T7503-1 Dual PCM Codec with Filters Features Description • +5 V only For those applications where tight parametric performance is less critical, a spec relaxed T7503-1 dual codec is offered. This device is suitable for

Contextual Info: A T & T MELCC I C btE II • DDSODSb DDPTtbR 1R8 M A T T ä ATsT June 3" 1993 ^ M ic r o e le c tr o n ic s AT&T HSM144xD Data Pump Chip Sets (14,400 bits/s Data/FAX, ROM Code MA) Introduction The AT&T HSM144xD Data Pump Chip Sets allow modem designers to build high-speed, fully-featured

Contextual Info: iH Data Sheet May 1995 A T & T Microelectronics DSP1616-X30 Digital Signal Processor 1 Features 2 Description • Optimized for digital cellular applications with a bit manipulation unit for higher signal coding efficiency ■ 20 ns, 25 ns, and 30 ns instruction cycle times

zener diode c24 5t

Contextual Info: Microelectronics Advance Data Sheet June 1996 Lucent Technologies Bell Labs Innovations T7234 Single-Chip NT1 SCNT1 Euro-LITE Transceiver Features Description • U- to S/T-interface conversion for ISDN basic rate (2B+D) systems — Integrated U- and S/T-interfaces

DSP32C-F35-080

Abstract: DSP32C-R35-080 pir 815 OXE800 we dsp32 dsp32c DSP32C-R35-050 Serial memory ic DSP3207 t17c
Contextual Info: mAT&T Data Sheet June 1995 ; ’^ ^ ^ ’ Microelectronics DSP32C Digital Signal Processor with External Memory Interface Introduction Description AT&T is an industry leader in floating-point digital signal processing. AT&T's DSP32 architecture was introduced in 1985 and is now the accepted stan­

Contextual Info: Data Sheet March 1997 microelectronics group Lucent Technologies Bell Labs Innovations TMPR28051 STS-1/AU-3 Mapper Features Configurable TU-12 slot selection for E1 drop Overall Device: Detects AU-3 loss of H4 multiframe, AIS-P, and RDI-P • PLL-free receive operation when used with Lucent

T7290A

Abstract: T7689
Contextual Info: Data Sheet May 1998 m icroelectronics group Lucent Technologies Bell Labs Innovations T7689 5.0 VT1 Quad Line Interface Features Description • Four fully integrated T 1 line interfaces ■ Includes all driver, receiver, equalization, clock recovery, and jitter attenuation functions