|
Contextual Info: £ XC5200 Field Programmable Gate Arrays x ilin x August 6,1996 Version 4.01 Preliminary Product Specification Features • Fully supported by XACTsfep Development System - Includes complete support for XACT-Performance™, X-BLOX™, Unified Libraries, Relationally Placed
|
OCR Scan
|
xc5200pq100vq100tq144+6pg156xc5202xc5204xc5210xc5215pq160
|
PDF
|
80C31 instruction set
Abstract: EXIF-91h
Contextual Info: DS80C320 DALLAS SEMICONDUCTOR FEA TU R ES • 80C32-Compatible - Pin-compatible Standard 8051 instruction set - F our8-bit I/O ports Three 16-bit timer/counters 256 bytes scratchpad RAM Multiplexed address/data bus Addresses 64K bytes ROM and 64K bytes RAM
|
OCR Scan
|
ds80c32080c32-compatible10x10x2abl4130+444-pin2bl413g80c31 instruction setexif-91h
|
PDF
|
78078YGF
Abstract: BS1471 P721H
Contextual Info: D A TA SHEET MOS INTEGRATED CIRCUIT //IPD78074Y, 78075Y, 78076Y, 78078Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The iiPD78074Y, 78075Y, 78076Y, and 78078Y are the same as the corresponding product without the Y suffix except that the PC bus control function has been added. These products are ideal for AV products.
|
OCR Scan
|
upd78074yupd78075yupd78076yupd78078y+9iipd78074y78075y78076y78078yupd78p078eeu-85878078ygfbs1471p721h
|
PDF
|
DALLAS DS80C320
Abstract: DS80C320-QCG T movx 80C32 DS80 DS80C320 DS80C320-FCG DS80C320-FNG DS80C320-QCG QDG775S
Contextual Info: DS80C320 DALLAS SEMICONDUCTOR FEA TU R ES • 80C32-Compatible - Pin-compatible Standard 8051 instruction set - F our8-bit I/O ports Three 16-bit timer/counters 256 bytes scratchpad RAM Multiplexed address/data bus Addresses 64K bytes ROM and 64K bytes RAM
|
OCR Scan
|
ds80c32080c32-compatible16-bitabl4130+12000777a44-pin2bl413qdallas ds80c320ds80c320-qcg tmovx80c32ds80ds80c320-fcgds80c320-fngds80c320-qcgqdg775s
|
PDF
|
C101E
Contextual Info: MfciE » SEMICONDUCTOR □ 2 5 0 ^ 2 ^ 5 1 - 11 CYPRESS SEMICONDUCTOR Functional Description • BiCM O S for optimum speed/power • High speed max. — 2,5 ns tpu TTL-to-ECL T he CY10/101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-performance
|
OCR Scan
|
000775bcy10e383cy101e383383-2jc+210e383--3jcc101e
|
PDF
|
TSO-C148
Abstract: RCA 719 RMS 01 EBT GR-253-CORE PM5346 PM5348 11CT40 PM5348R philips ferrite core 4b1
Contextual Info: PM S ta n d a r d P r o d u c t PM C-950919 PM C-Sierra, Inc. JSSUE6 PM5 3 4 8 S/UNI-DUAL SA TURN USER NETWORK INTERFACE FEATURES • Single chip dual ATM User-Network Interface operating at 155.52 and 51.84 Mbit/s. • Provides essential hardware and software compatibility with industry-standard
|
OCR Scan
|
pm5348s/un/-dualpmc-950919pm5346ci0041ci1+8tso-c148rca 719rms 01 ebtgr-253-corepm534811ct40pm5348rphilips ferrite core 4b1
|
PDF
|