000541B Search Results

Contextual Info: XC7354 54-Macrocell CMOS EPLD Product Specifications Features The Universal Interconnect Matrix connects the Function Blocks to each other and to all input pins, providing 100% connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and

Contextual Info: F I Standard Product PMC-941033 ISSUES ^ I V i r " 1 PMC-Sierra, Inc. I V 1 ^ » _ _ , PM5347 S/UNI-PLUS SATURN USER NETWORK INTERFACE 155 Mbit/s&51 Mbit/s, 'PLUS' FE A TU R E S • Monolithic Saturn User Network Interface that implements the ATM physical layer

Contextual Info: Lattice ispLSrand pLSI 3256E Semiconductor I Corporation High Density Programmable Logic Feature Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGI — 256 I/O Pins — 11000 PLD Gates — 512 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, Stat

GM71C4400

Abstract: CLZ80 GM71C4400C V888 OF100
Contextual Info: @ LG Semicon. Co. LTD Description Features The GM71C4400C/CL is the new generation dynam ic R A M o rg an ized 1,048,576 x 4 b it. GM71C4400C/CL has realized higher density, higher perform ance and various functions by utilizing a d v a n c e d CM OS p ro c e s s te c h n o lo g y . T he

h05u

Abstract: NJU7307L CT1627 Stereo Graphic Equalizer th02 HJU7307B NJU7307 NJU7307G
Contextual Info: N JL J~7 3 O 7 11-BAND EVR F OR GRAPHIC GENERAL DESCRIPTION The NJU7307 is a electrical variable resistor EVR incorporated 11-band each for left and right channels, especialy apply to the stereo type graphic equalizer. It consists of input controller, channel/band/IeveI