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Part Manufacturer Description Datasheet BUY
HSP45106JC-33Z Intersil Corporation 16-Bit Numerically Controlled Oscillator; PLCC84; Temp Range: 0° to 70° visit Intersil Buy
HSP45116AVC-52 Intersil Corporation Numerically Controlled Oscillator/Modulator; MQFP160; Temp Range: 0° to 70° visit Intersil Buy
HSP45116DB-EVAL Intersil Corporation Numerically Controlled Oscillator/Modulator; ; Package: 160-Eval Board visit Intersil
HSP45116AVC-52Z Intersil Corporation Numerically Controlled Oscillator/Modulator; MQFP160; Temp Range: 0° to 70° visit Intersil Buy
HSP45106JC-25Z Intersil Corporation 16-Bit Numerically Controlled Oscillator; PLCC84; Temp Range: 0° to 70° visit Intersil Buy
HSP45106JC-25 Intersil Corporation 16-Bit Numerically Controlled Oscillator; PLCC84; Temp Range: 0° to 70° visit Intersil Buy

vhdl code numeric controlled oscillator pipeline

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4 tap fir filter based on mac vhdl code

Abstract: transposed fir Filter VHDL code Local Oscillator Analog (RF) Digital Analog (Audio) Multiply Decimation Low Pass FIR Filter Multiply Decimation Low Pass FIR Filter Numeric Controlled Oscillator I data , implemented in the VirtexTM and Virtex-II series and SpartanTM-II family of FPGAs. The VHDL reference design , pipeline registers. The input registers are not required, because high fan-out input signals can be , ) in Xilinx FPGAs. One approach is to use the case statement. With this approach, the code would
Xilinx
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verilog code for 2D linear convolution

Abstract: verilog code for GPS correlator . 45 Numerically Controlled Oscillator , Controlled Oscillator PCI Bus Master (EC200) 32-Bit PCI Bus M/T PCI Bus Target (EC100) PowerPC Bus Arbiter , in numeric sequence). 1 Profiles Table 2. AMPP Megafunction Applications (Part 1 of 2 , used without risk of changes during design processing. Although VHDL and Verilog HDL files are available from most partners, a source code license is usually more expensive than a post-synthesis netlist
Altera
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verilog code for 2D linear convolution verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter M-CAT-AMPP-02 EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50

free vHDL code of median filter

Abstract: free verilog code of median filter . 46 Numerically Controlled Oscillator , Controlled Oscillator PCI Bus Master (EC200) 32-Bit PCI Bus M/T PCI Bus Target (EC100) PowerPC Bus Arbiter , in numeric sequence). Table 1. AMPP Megafunction Applications (Part 1 of 2) Processors & , used without risk of changes during design processing. Although VHDL and Verilog HDL files are available from most partners, a source code license is usually more expensive than a post-synthesis netlist
Altera
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free vHDL code of median filter verilog code for UART with BIST capability verilog code for 2D linear convolution filtering vhdl median filter 8051 interface ppi 8255 verilog median filter

pcf 7947

Abstract: pcf 7947 at Oscillators . 61 Oscillator VHDL Example , design examples in this manual were created with Verilog and VHSIC Hardware Description Language (VHDL , , Virtex-E, Virtex-II and XC5200 devices. Xilinx equally endorses both Verilog and VHDL. VHDL may be more , Verilog. 5 Using VHDL , Entry Recommendations . 3 Using RTL Code
Xilinx
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pcf 7947 pcf 7947 at ieee floating point multiplier vhdl future scope VHDL Coding for square pulses to drive inverter 8 BIT ALU using modelsim want abstract x8505 XC4000XLA XC2064 XC3090 XC4005 XC5210 XC-DS501

Cyclone II DE2 Board DSP Builder

Abstract: verilog code for cordic algorithm for wireless la Pipeline Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . 8­11 Adding VHDL Dependencies to the Quartus II Project and ModelSim . . . . . , . . . . . . . . . . . . . 13­7 VHDL Entity Names Change if a Model is Modified . . . . . . . . . . , Pipeline Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Altera
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Cyclone II DE2 Board DSP Builder verilog code for cordic algorithm for wireless la vhdl code for a updown counter verilog code for cordic algorithm for wireless verilog code for CORDIC to generate sine wave simulink matlab PFC

4-bit AHDL adder subtractor

Abstract: amplitude demodulation matlab code Least Significant Bit Model File (.mdl) Most Significant Bit Multiplexer Numerically Controlled Oscillator Programmable Logic Device Programmer Object File Register Transfer Level Signed Binary , .56 Generate VHDL, Synthesize, Compile & Download the Design to the DSP Board .57 Specify Trigger , system-level design tools with VHDL synthesis, simulation, and Altera development tools. The DSP Builder , generates VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation. High-Speed
Altera
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4-bit AHDL adder subtractor amplitude demodulation matlab code pulse amplitude modulation matlab code a6w 58 A4w sd vhdl code for digit serial fir filter OEM2002

16 BIT ALU design with verilog/vhdl code

Abstract: verilog code for barrel shifter Using Oscillators (VHDL) . VHDL Oscillator , Internet Files Description All VHDL source code only (no scripts, compilation, or implementation , M1_HDL_source1 All VHDL and Verilog source code only (no scripts, compilation, or implementation files , MB) 14.9 MB M1_XSI_HDL2 All VHDL and Verilog source code, scripts, compilation, and , only the VHDL or Verilog source code, and not the compilation and implementation files. If you want to
Xilinx
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16 BIT ALU design with verilog/vhdl code verilog code for barrel shifter verilog code for 4-bit alu with test bench verilog code for barrel shifter and efficient add verilog code for ALU verilog code for ALU implementation XC4000

16 BIT ALU design with verilog/vhdl code

Abstract: verilog code for barrel shifter ) . Oscillator VHDL Example . Oscillator Test , Directory/Location M1_VHDL_source1 Internet Files Description All VHDL source code only (no scripts , VHDL and Verilog source code only (no scripts, compilation, or implementation files) 1 , in this manual were created with Verilog and VHSIC Hardware Description Language (VHDL); compiled , equally endorses both Verilog and VHDL. VHDL may be more difficult to learn than Verilog and usually
Xilinx
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8 BIT ALU design with verilog/vhdl code 16x4 ram vhdl vhdl code for 16 bit barrel shifter ieee floating point alu in vhdl spartan 3a verilog code for jk flip flop

matlab programs for impulse noise removal

Abstract: verilog code for cordic algorithm for wireless numerically controlled oscillator. f For more information, refer to the FFT MegaCore Function User , , and a numerically controlled oscillator (NCO) that allow you to quickly create designs for digital , hardware description language (HDL) such as VHDL or Verilog HDL. Thus, the same FPGA can implement a DSL , Simulink to Design Algorithm Write Assembly or C Code Add DSP Libraries Use DSP Processor , implemented in C/C+ or assembly code with an integrated development environment that provides design
Altera
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matlab programs for impulse noise removal block interleaver in modelsim matlab programs for impulse noise removal in image vhdl code for cordic vhdl code to generate sine wave PLDS DVD V9

verilog code for barrel shifter

Abstract: 16 BIT ALU design with verilog/vhdl code ) . 5-47 VHDL Oscillator Example . 5-48 , Internet Files Description All VHDL source code only (no scripts, compilation, or implementation , M1_HDL_sourcea All VHDL and Verilog source code only (no scripts, compilation, or implementation files , MB) 14.9 MB M1_XSI_HDLb All VHDL and Verilog source code, scripts, compilation, and , only the VHDL or Verilog source code, and not the compilation and implementation files. If you want to
Xilinx
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full vhdl code for alu verilog code for implementation of rom vhdl code for 8 bit barrel shifter vhdl code for multiplexer 16 to 1 using 4 to 1 32 BIT ALU design with verilog/vhdl code verilog code for 32 BIT ALU implementation

verilog code for barrel shifter

Abstract: decoder in verilog with waveforms and report ) . 5-44 Oscillator VHDL Example . 5-45 , Directory/Location M1_VHDL_sourcea Internet Files Description All VHDL source code only (no scripts , (size: 129 KB) 497 KB All VHDL and Verilog source code only (no scripts, compilation, or , were created with Verilog and VHSIC Hardware Description Language (VHDL); compiled with various , and VHDL. VHDL may be more difficult to learn than Verilog and usually requires more explanation
Xilinx
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decoder in verilog with waveforms and report fd32ce future scope of barrel shifter structural vhdl code for multiplexers vhdl projects abstract and coding 32 bit barrel shifter-verilog code

real time simulink wireless

Abstract: quadrature amplitude modulation a simulink model . . . . . . . . . . . . . . . . 3­23 Displaying the Pipeline Depth . . . . . . . . . . . . . . . . , . . . . . . . . . . . . 8­11 Adding VHDL Dependencies to the Quartus II Project and ModelSim . . . , . . . . . . . . . . . . . . . . . . . B­8 VHDL Entity Names Change if a Model is Modified . . . . . , Date Ordering Code Description 9.1 November 2009 IPT-DSPBUILDER Device Family Support DSP , . HDL import of VHDL or Verilog HDL design entities and HDL defined in a Quartus II project file
Altera
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real time simulink wireless quadrature amplitude modulation a simulink model EP2C35F672C6 de2 board using rs232 and keyboard to display advantages and disadvantages simulation of UART using verilog verilog code pipeline square root

ATM SYSTEM PROJECT- ABSTRACT

Abstract: 8 BIT ALU design with verilog/vhdl code . 6­3 Instantiating Altera Megafunctions in HDL Code , . 6­7 Inferring Multiplier and DSP Functions from HDL Code . 6­7 Multipliers-Inferring the lpm_mult Megafunction from HDL Code , Megafunctions from HDL Code . 6­10 Inferring Memory Functions from HDL Code
Altera
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ATM SYSTEM PROJECT- ABSTRACT alu project based on verilog ieee floating point multiplier vhdl verilog code for serial multiplier verilog code voltage regulator C102 M102 transistor

ATM SYSTEM PROJECT- ABSTRACT

Abstract: full subtractor circuit using xor and nand gates . 2­82 Assignments Made in HDL Source Code in Bottom-Up Flows , . 6­3 Instantiating Altera Megafunctions in HDL Code , . 6­7 Inferring Multiplier and DSP Functions from HDL Code . 6­7 Multipliers-Inferring the lpm_mult Megafunction from HDL Code , Megafunctions from HDL Code
Altera
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full subtractor circuit using xor and nand gates NEC MEMORY nec Microcontroller metal detector service manual circuit diagram of 8-1 multiplexer design logic SIMPLE digital clock project report to download

MZ80 sensor

Abstract: crt monitor circuit diagram intex 171 D SD Q F1 EC RD K (CLOCK) 1 H' F' X Multiplexer Controlled by Configuration , code. Internal Bi-Directional Bussing Most system-level designs contain a bi-directional data bus , outputs are controlled by an output enable signal. The XC4000-Series FPGAs provide up to one , EDIF, SDF, VHDL (Vital) and Verilog. Powerful, Simple Flows The M1 development process insured that
Xilinx
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MZ80 sensor crt monitor circuit diagram intex 171 8086 microprocessor based project on weight AT89C51 opcode SL100 pin configuration generation of control signals in 89c51 micro XC4000-S PCI32 XC3000 XC5000

AT 2005B Schematic Diagram

Abstract: SDC 2005B . 7­2 Instantiating Altera Megafunctions in HDL Code , . 7­5 Inferring Altera Megafunctions from HDL Code . 7­6 lpm_mult-Inferring Multipliers from HDL Code . 7­6 altmult_accum & altmult_add-Inferring Multiply-Accumulators & Multiply-Adders from HDL Code . 7­9 altsyncram & altdpram-Inferring RAM Functions from HDL Code
Altera
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AT 2005B Schematic Diagram SDC 2005B led matrix 8x64 message circuit 16X2 LCD vhdl CODE AT 2005B AT 2005B at

ATM SYSTEM PROJECT- ABSTRACT

Abstract: led matrix 8x64 message circuit . 7­2 Instantiating Altera Megafunctions in HDL Code , . 7­5 Inferring Altera Megafunctions from HDL Code . 7­6 lpm_mult-Inferring Multipliers from HDL Code . 7­6 altmult_accum & altmult_add-Inferring Multiply-Accumulators & Multiply-Adders from HDL Code . 7­9 altsyncram & altdpram-Inferring RAM Functions from HDL Code
Altera
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TB 25 Abc FAN 763 schematic adata flash disk scf 4242 EPE PIC TUTORIAL v2 part 1 sdc 339 PWM

circuit diagram of 8-1 multiplexer design logic

Abstract: mtbf stratix 8000 Source Code Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 Assignments Made in HDL Source Code in , Megafunctions in HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , and DSP Functions from HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Inferring Multipliers from HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Altera
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mtbf stratix 8000 UART using VHDL MTBF calculation excel design of FIR filter using vhdl abstract altera cyclone 3 sequential logic circuit experiments QII5V1-10

LVDS connector 26 pins LCD m tsum

Abstract: simple microcontroller using vhdl Determining Which Partitions Are Resynthesized Due to Source Code Changes . . . . . . . . . . . Forcing Use , . . . . . . . . . 2-65 Assignments Made in HDL Source Code in Bottom-Up Flows . . . . . . . . . . .
Altera
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LVDS connector 26 pins LCD m tsum simple microcontroller using vhdl DDR3 sdram pcb layout guidelines IC 74 HC 193 m104a electrical engineering projects

transistor full 2000 to 2012

Abstract: 0x020F30DD . . . . . . . . . . . . . . . . . . . . . . Resynthesis Due to Source Code Changes . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Assignments Made in HDL Source Code in , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 Using VHDL . . . . . . . . .
Altera
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transistor full 2000 to 2012 0x020F30DD finder 15.21 catalog logic pulser ic 741 comparator signal generator QII51002-9
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