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verilog module of byte comparator

Catalog Datasheet MFG & Type PDF Document Tags

16 byte register VERILOG

Abstract: vhdl codings for fast page mode dram controller /receive capability · 32-byte burst size for efficient use of 80C300 internal FIFO · Automatic , shown in Figure 10. Details of the DMA register implementation may be found in the Verilog source file , TARTO is a Verilog module that checks for the Master Abort condition. DevSelTO is asserted if DEVSEL , and pinout capabilities of the QL2009 device are key to providing the necessary interface , accommodate the stringent system timing requirements of the 33 MHz PCI bus. All required PCI Configuration
QuickLogic
Original
16 byte register VERILOG vhdl codings for fast page mode dram controller pci master verilog code pc motherboard schematics AN21BUF2 AN21 QAN15

verilog code of 8 bit comparator

Abstract: vhdl code for 4 channel dma controller registers · Simultaneous transmit/receive capability · 32-byte burst size for efficient use of , Verilog source code. Figure 4 indicates the external signals of the FPGA, connecting to the PCI Bus and , synthesized from Verilog. Also on this page are the Target Time-out module (TARTO) and Latency Counter , Notes TARTO is a Verilog module that checks for the Master Abort condition. DevSelTO is asserted if , logic and pinout capabilities of the QL24x32B device are key to providing the necessary interface
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verilog code of 8 bit comparator vhdl code for 4 channel dma controller pci schematics pin vga CRT pinout H3C1 1 wire verilog code

verilog code for 4-bit alu with test bench

Abstract: to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of , result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress , System-on-ChipTM, and WarpTM are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or
Cypress Semiconductor
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verilog code for 4-bit alu with test bench

FSP250-60GTA

Abstract: fsp250-60gta power supply schematic trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their , applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to , liability arising out of the application or use of any information, product, or service described herein , the latest version of device specifications before relying on any published information and before
Altera
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FSP250-60GTA fsp250-60gta power supply schematic power supply fsp250-60gta fsp250-60 FSP250 manual FSP250-60gta manual P25-09565-00 RS-232 D-85757

verilog code for correlator

Abstract: vhdl code for complex multiplication and addition Template-Sample Verilog HDL instantiation of the module in the megafunction wrapper file. , . Quartus II Language Templates Many of the Verilog HDL and VHDL examples in this document correspond with , . Verilog HDL module declaration file that can be used when instantiating the megafunction as a black box , instantiation of the subdesign in the megafunction wrapper file. _bb.v Black box Verilog HDL Module Declaration-Hollow-body module declaration that can be used in Verilog HDL designs to specify
Altera
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QII51007-10 verilog code for correlator vhdl code for complex multiplication and addition vhdl code CRC vhdl code for accumulator vhdl code of carry save multiplier vhdl code for lvds driver

DW01A

Abstract: gdr5 . //////////////////////////////////////////////////////////////// 34. // Lump a Small Amount of Delay on the Outputs of this Module 35 , independently and not within the context of the Verilog code above. The resulting gate level circuit matched the , ; ////////////////////////////////////////////////////////////////////////////// ; // Subroutine: P1_GET_HALFWORD ; // ; // Issues a pair of Byte DMA Read[s], increments the source and , ; ////////////////////////////////////////////////////////////////////////////// ; // Subroutine: P2_GET_HALFWORD ; // ; // Issues a pair of Byte DMA Read[s], increments the source and , of the comparator that was designed for the MXT3010B/C, which did not correctly model the signed
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MXT3010EP-A DW01A gdr5 F29E DW01 FFF10000 MXT3010 AS3010 MXT3010EP

vhdl code for 4 channel dma controller

Abstract: verilog code of 8 bit comparator schematic that represents your Verilog or VHDL file(s). Of course, you may also use a Verilog or VHDL file , . Step-by-step Project Setup Regardless of whether you intend on designing with schematics, VHDL, Verilog, or , appropriate section of the Verilog (.V) file is shown here. // * beginning of user-modifiable , . From the Turbo Writer menu, click on File > Open. Then choose VHDL or VERILOG from the `List Files of , designing your top-level block in Verilog or VHDL, you will be using a .SC file to specify the pinout of
QuickLogic
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QL5032 vhdl code dma controller latgn pci to pci bridge verilog code asynchronous fifo vhdl verilog code 8 bit LFSR dell core i3

verilog hdl code for parity generator

Abstract: verilog code for half adder using behavioral modeling principal design entity in the Verilog language is a module. A module consists of the module name, its , of a module are illustrated in the following figure. Verilog Reference Guide 3-1 Verilog , efficient implementation. · Chapter 9, "Verilog Syntax," contains syntax descriptions of the Verilog , Figure 1-1 Foundation Express Design Process Foundation Express supports a majority of the Verilog constructs. For exceptions, see the "Unsupported Verilog Language Constructs" section of the "Verilog
Xilinx
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verilog hdl code for parity generator verilog code for half adder using behavioral modeling verilog code mealy for vending machine drinks vending machine circuit SR flip flop using discrete gates vending machine hdl XC2064 XC3090 XC4005 XC5210 XC-DS501

4x4 unsigned multiplier VERILOG coding

Abstract: 32x32 multiplier verilog code //Module: //Description: // // // Device: TWO_BYTE_CLK Verilog Submodule DCM for 2-byte GT Virtex-II Pro , bitstream byte boundary when minus-comma is detected. Selects realignment of incoming serial bitstream on , bit of the 10-bit encoded TXDATA bus for each byte specified by the byte-mapping section. If 8B/10B , position of the first byte depends on selected TX data path width. 1 Specifies whether to insert error in , Description True/False controls the alignment of detected commas within the transceivers 2-byte wide data path
Xilinx
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4x4 unsigned multiplier VERILOG coding 32x32 multiplier verilog code 12v relay interface with cpld in vhdl MULT18X18 verilog/verilog code for lvds driver 80C31 instruction set UG012 PCI64 DO-DI-PCI64-IP

verilog code for lvds driver

Abstract: parallel to serial conversion vhdl from lvds module first extracts the embedded high speed clock from the Input Serial Data Stream by means of the , . Following definition, a VHDL or Verilog module that instantiates the desired sysHSI primitive is created , `Generate" creates a VHDL (module name .vhd) or Verilog (module name.v) file in the working directory that , code. The following section provides examples of source code generated by the Module/IP Manager. These , . Source Code Examples Generated by Module/IP Manager Below are VHDL and Verilog examples generated by
Lattice Semiconductor
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10B12B 8B10B verilog code for lvds driver parallel to serial conversion vhdl from lvds vhdl code for clock and data recovery vhdl code for deserializer parallel to serial conversion vhdl IEEE format TN1020 TN1000 1-800-LATTICE

verilog code for fixed point adder

Abstract: vhdl code for BCD to binary adder .; RenoirTM, MonetTM, and PackagedPowerTM are trademarks of Mentor Graphics Corporation. Verilog® and , . . . . . . . . . . . . . Parameter Override During Instantiation of Module . . . . . . . . . . . . , 7-34 8. Verilog and Synthesis of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . , trademarks of Exemplar Logic, Inc. LeonardoSpectrumTM, LeonardoInsightTM, FlowTabsTM, HdlInventorTM, SmartScriptsTM, P&RIntegratorTM, DesktopASICTM, XlibCreatorTM, SynthesisWizardTM, and MODGENTM are trademarks of
Lattice Semiconductor
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verilog code for fixed point adder vhdl code for BCD to binary adder vhdl code for 8-bit BCD adder vhdl code for 8 bit bcd to seven segment display

VHDL tb_user_corei2c.vhd RTL user testbench

Abstract: pmbus verilog S P Stop Start Figure 1-2 · Serial Interface Byte Transfer A user of CoreI2C must configure , read data byte 1 0 0 0 Switched to not-addressed SLV mode; no recognition of own SLA , States of America Part Number: 50200090-5 Release: November 2009 No part of this document may be copied or reproduced in any form or by any means without prior written consent of Actel. Actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or
Actel
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VHDL tb_user_corei2c.vhd RTL user testbench pmbus verilog CORE8051 rtax1000 APA075 I2C master controller VHDL code

XAPP581

Abstract: asynchronous fifo vhdl xilinx Fibre Channel rate of 1.0625 Gb/s. · · Provides single-port instantiation with a 2-byte user , Block Diagram The comma alignment module attempts to realign the data to a proper byte boundary so that , that the first byte of a CLK_COR_SEQ appears on the LSB, or byte 0, on the 20-bit internal data path , setting the comma character to match the second byte of CLK_COR_SEQ. XAPP581 (v1.0) October 6, 2006 , the comma alignment module and decodes the received data into 2 bytes of data in parallel. The 8B
Xilinx
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XAPP572 asynchronous fifo vhdl xilinx vhdl code fc 2 verilog module of byte comparator on error correction code in fpga in vhd RXRECCLK XC2VP7-FF672-6 PPC405 UG035 UG024 UG033

vhdl code for watchdog timer

Abstract: UNSIGNED SERIAL DIVIDER using verilog can commence reception of a second byte before a previously received byte has been read from the , commence reception of a second byte before a previously received byte has been read from the receive , ultra high performance, speed optimized soft core of a single-chip 8bit embedded controller dedicated , standard 8051 8bit microcontroller. There are two configurations of DP8051XP: Harward where internal data , and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy
Digital Core Design
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DP80390CPU DP80390 vhdl code for watchdog timer UNSIGNED SERIAL DIVIDER using verilog ieee single precision floating point alu in vhdl verilog code for floating point division vhdl code for i2c Slave verilog code for cordic algorithm sine cosine DP80390XP

verilog code for 32-bit alu with test bench

Abstract: verilog code for single precision floating point multiplication high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for , configurations of DR80390XP: Harward where external data and program buses are separated, and von Neumann with , All trademarks mentioned in this document are trademarks of their respective owners. with complete set of tests allowing easy package validation at each stage of SoC design flow. CPU KEY FEATURES , (DPTR) for faster memory blocks copying Advanced INC & DEC modes Auto-switch of current DPTR Up
Digital Core Design
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80C390 DR8051CPU DR8051 verilog code for 32-bit alu with test bench verilog code for single precision floating point multiplication 8051 16bit division collision detector vhdl 8051 16bit addition, subtraction 80C51 DR8051XP

verilog code for single precision floating point multiplication

Abstract: verilog code for floating point division receiver is double-buffered, meaning it can commence reception of a second byte before a previously , double-buffered, meaning it can commence reception of a second byte before a previously received byte has been , high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for , configurations of DR8051XP: Harward where external data and program buses are separated, and von Neumann with , All trademarks mentioned in this document are trademarks of their respective owners. with complete
Digital Core Design
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DR80390CPU DR80390 vhdl code for cordic algorithm IEEE754 vhdl code 32 bit risc code interfacing 8051 with eeprom c source code

vhdl code for cordic

Abstract: 8051 16bit addition, subtraction document are trademarks of their respective owners. Source code: VHDL Source Code or/and VERILOG , data flow control. This module is directly connected to Opcode Decoder and manages execution of all , performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with , % binarycompatible with the industry standard 80C390 8-bit microcontroller. There are two configurations of , mentioned in this document are trademarks of their respective owners. with complete set of tests
Digital Core Design
Original
vhdl code for cordic verilog code for cordic vhdl code 64 bit FPU verilog code for 32 BIT ALU implementation verilog code for cordic algorithm ieee floating point verilog

i2c interfacing with 8051 asm code

Abstract: verilog code for floating point multiplication reception of a second byte before a previously received byte has been read from the receive register , ultra high performance, speed optimized soft core of a singlechip 8-bit embedded controller dedicated , standard 80390 & 8051 8-bit microcontroller. There are two configurations of DP80390XP: Harward where , and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow. All trademarks mentioned in this document are
Digital Core Design
Original
i2c interfacing with 8051 asm code verilog code for floating point multiplication 3 bit right left shift register verilog HDL prog verilog code of sine rom ieee floating point alu in vhdl vhdl code for i2c master DP8051CPU DP8051

verilog code for 32-bit alu with test bench

Abstract: ieee floating point alu in vhdl data flow control. This module is directly connected to Opcode Decoder and manages execution of all , performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with , % binarycompatible with the industry standard 8051 8bit microcontroller. There are two configurations of DR8051XP , this document are trademarks of their respective owners. with complete set of tests allowing easy package validation at each stage of SoC design flow. CPU KEY FEATURES 100% software compatible with
Digital Core Design
Original
verilog code for implementation of eeprom verilog code for 32 BIT ALU multiplication verilog code for floating point unit 8 BIT ALU design with verilog interfacing 8051 with eprom and ram OPCODE SHEET FOR 8051 MICROCONTROLLER

GR-253-CORE

Abstract: synchronous fifo design in verilog Significant bit Most Significant Byte New Data Flag Out Of Frame Personal Computer Path Overhead Receive , VHDL design file (.vhd); ­ A Verilog design file (.v); Sample Verilog instantiation of Black Box , below) that indicate the type of byte being processed on the next clock pulse. I mtxval indicates , . Implementing the rest of your system using the AHDL, VHDL, or Verilog HDL. 4. Compiling your design and , Design Entry/Synthesis Tool list. 5. Depending on the type of output file you want, specify Verilog
Altera
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GR-253-CORE synchronous fifo design in verilog
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