NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist , xramwr docddatai docddatao docdclk stop pmm Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist One Year license for , dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been , unit makes DR8051CPU DR8051CPU core perfect for portable equipment where low power consumption is mandatory. ... | Original |
7 pages, |
32 BIT ALU design with vhdl 80C51 design IP Uarts using verilog HDL DR8051 DR8051CPU DR8051XP vhdl code for 8 bit common bus vhdl code for alu low power vhdl code of floating point unit 3 bit alu using verilog hdl code 8 BIT ALU design with vhdl code 8051 8bit microcontroller DR8051CPU abstract |
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| Abstract: , data sheet, instruction set details Design File Formats EDIF netlist, ngo, VHDL, Verilog RTL source , , Verilog Reference designs Example design, & application notes assembler programs Additional Items None Simulation Tool Used VHDL and Verilog EDA simulators Support Support provided by Digital Core Design · · · Four 8-bit I/O Ports Interface for additional Special Function Registers Fully , None None None Notes: 1. Utilization numbers for Virtex are in CLB slices. 2. Assuming all core ... | Original |
4 pages, |
8051 16bit addition, subtraction 8051 using I2C BUS ARITHMETIC COPROCESSOR DR8051 OPCODE 8051 MICROCONTROLLER ram memory testbench vhdl uart vhdl fpga 4 BIT ALU design with verilog vhdl code vhdl code for data memory verilog code for TCON ieee alu in vhdl interrupt controller verilog code DR8051 abstract |
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| Abstract: Single Design license for VHDL, Verilog source code called HDL Sour- ce Encrypted, or plain text , Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG , is typically used for main code and constants. This part of the code is usually implemented as ROM , configurable. For timing-critical applications whole program code can be implemented as on-chip ROM and (or) RAM and executed without Wait-States, but for some other applications whole program code can be ... | Original |
10 pages, |
vhdl code of floating point unit 8 BIT ALU design with vhdl code 80C51 APEX20K APEX20KC APEX20KE DP8051 DP8051CPU DP8051XP FLEX10KE vhdl code for accumulator VHDL code for floating point addition verilog code for TCON DP8051CPU abstract |
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| Abstract: Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test , VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist , Memory located in address space between 0kB and 1kB is typically used for BOOT code with system , located in address space between 60kB and 64kB is typically used for timing critical part of the code , between 1kB and 60kB, and above 64 kB is typically used for main code and constants. This part of the ... | Original |
9 pages, |
32 BIT ALU design with vhdl 80C51 DP80390 DP80390CPU DP80390XP DP8051 DP8051CPU DP8051XP mip* 282 vhdl code for accumulator vhdl code for alu low power program uart vhdl fpga 16 bit single cycle mips vhdl DP80390CPU abstract |
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| Abstract: 12 months. Single Design license for VHDL, Verilog source code called HDL Source , memory Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text , for BOOT code with system initialization functions. This part of the code is typically implemented as , in address space between 1kB and 60kB is typically used for main code and constants. This part of , Memory spaces are fully configurable. For timing-critical applications whole program code can be ... | Original |
9 pages, |
8051 16bit addition, subtraction 80C51 DP80390 DP80390CPU DP80390XP DP8051 DP8051CPU DP8051XP mip* 282 verilog code for ALU verilog code for i2c communication fpga vhdl code of floating point unit 32 BIT ALU design with vhdl DP8051CPU abstract |
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| Abstract: peripherals Variable length code fetch and MOVC to access fast/slow program memory Dual data pointer for , ROM Deliverables · VHDL or Verilog HDL source code · Post-synthesis EDIF netlist , an option. The microcode-free, strictly synchronous design was developed for reuse in ASICs and , bi-directional I/O port with separated inputs and outputs Clock A pulse for internal clock counters and all synchronous circuits Hardware reset Resets the device when this pin is held high for two clock cycles ... | Original |
5 pages, |
ASM51 80C31 SAB80C537 Evatronix R80515 evatronix R80515 R80515 abstract |
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| Abstract: netlist. For each RAM256X9 RAM256X9 primitive initialized with code, a defparam (in verilog) or generic map (in , contains verilog models for RAMs and ACTgen project APA300 APA300_Core8051/code/ contains Keil uV2 project and , microcontroller. For this design, the SRAM inside the APA300 APA300 device is used for CODE, XDATA, and Data memory , ) · CODE 64 kbytes x 8 bits wide, used for program storage and interrupt vectors · XDATA , core) and external memory for special function registers CODE, DATA, and XDATA memory spaces are ... | Original |
17 pages, |
APA075-PQ208 ASM51 80C31 transistor dk51 datasheet ISA-Actel51 DK51 transistor vhdl code for 8 bit ram APA300 datasheet APA300-pq208 FLASHPRO LITE CORE8051 APA300 dk51 AC213 APA300 AC213 abstract |
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| Abstract: DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text , , Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist One Year license , for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed , makes DR80390 DR80390 core perfect for portable equipment where low power consumption is mandatory. DR80390 DR80390 , seven times more slowly than the original implementation for no performance penalty. DR80390 DR80390 is ... | Original |
8 pages, |
80C51 DR80390 DR80390CPU DR80390XP DR8051 DR8051CPU DR8051XP verilog code power management 32 bit ALU vhdl code microcontroller using vhdl 80C390 DR80390 abstract |
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| Abstract: limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source , SYMBOL DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted , high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for , core perfect for portable equipment where low power consumption is mandatory. DR8051 DR8051 soft core is , slowly than the original implementation for no performance penalty. DR8051 DR8051 is delivered with fully ... | Original |
8 pages, |
8051 8bit microcontroller 80C51 DR80390 DR80390CPU DR80390XP DR8051 DR8051CPU DR8051XP processor control unit vhdl code VHDL code for floating point addition 8051 16bit addition, subtraction DR8051 abstract |
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| Abstract: Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called , Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG , for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed , makes DR80390 DR80390 core perfect for portable equipment where low power consumption is mandatory. DR80390 DR80390 , seven times more slowly than the original implementation for no performance penalty. DR80390 DR80390 is ... | Original |
8 pages, |
DR80390CPU DR80390 80C51 8 bit data bus using vhdl 8 bit alu instruction in vhdl DR8051CPU DR8051XP OPCODE SHEET FOR 8051 MICROCONTROLLER ta 8268 uart verilog code vhdl code for 8 bit common bus 8 BIT ALU design with verilog 8 BIT ALU design with verilog code DR80390 abstract |
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