NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| PVF40GS10CMK45 | Freescale Semiconductor | CORTEXA5,DUAL USB,HS PHY | 
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| PVF40GS10CMK50 | Freescale Semiconductor | CORTEXA5,DUAL USB,HS PHY |
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| LPC1820FBD100,551 | NXP Semiconductors | Cortex-M3, 168 kB SRAM, HS USB with on-chip PHY, CAN, AES, SPIFI, SCT, SOT407-1 Package, Standard Marking, Tray Dry Pack, Bakeable, Single |
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| LPC1830FBD144,551 | NXP Semiconductors | Cortex-M3, 200 kB SRAM, 2 HS USB with on-chip PHY, Ethernet, CAN, AES, SPIFI, SCT, SOT486-1 Package, Standard Marking, Tray Dry Pack, Bakeable, Single |
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| LPC1820FBD144,551 | NXP Semiconductors | Cortex-M3, 168 kB SRAM, HS USB with on-chip PHY, CAN, AES, SPIFI, SCT, SOT486-1 Package, Standard Marking, Tray Dry Pack, Bakeable, Single |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ISI-220 ISI-220 BIST USB PHY Core BIST for Mixed-signal USB PHY The USB PHY is a Mixed-signal Core , in testing the USB PHY which is a mixed-signal block. It supports low/full/high speed. This is , PRELIMINARY PRODUCT INFORMATION USB Controller ISI-220 ISI-220 Test Pad USB PHY This type of pattern , initial conditions are known. The ISI-220 ISI-220 configures the USB PHY in the loopback mode. It then transmits , low/full/high speeds Related Products · ISI-200 ISI-200 USB Device PHY · ISI-205 ISI-205 USB Host PHY · ... | Original |
1 pages, |
usb PHY circuit for pseudo random generator random pattern generator ISI-220 ISI-220 abstract |
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| Abstract: capability Multiple clock input frequencies supported Allows USB PHY to operate from the system clock, eliminating � the need for an external crystal oscillator for the USB PHY Extremely small package , INTO ONE SOLUTION! 3.3V Reg USB Switch ULPI Signals to Controller Hi-Speed USB PHY BC 1.1 Spk Right En Spk Left En OSC Control REFCLK VBus OVP Full-Speed USB PHY or Power , OSC VBus OVP DP DM VBus Full-Speed USB PHY or Power Management SPI Signals to ... | Original |
2 pages, |
USB3346 USB connector life testing 334x USB3338 USB3333 usb esd usb-if USB334X usb phy USB3336 USB333x usb3330 USB3340 USB3343 datasheet abstract |
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| Abstract: product development cost Multiple clock input frequencies supported Allows USB PHY to operate from the system clock, eliminating the need for any external crystal oscillator for the USB PHY Ability , Solution! Ext. Reg. Hi-Speed USB PHY DP SMSC SOLUTION USB PHY USB Switch DP ULPI Signals to Controller DM DM OSC SPI Signals to Processor Control Full-Speed USB PHY , Oscillator USB Connector External VBus OVP IC VBus OVP DM Full-Speed USB PHY or Power ... | Original |
2 pages, |
USB332X ovp ic smsc usb3326 USB connector life testing USB3322 26MHz usb phy usb esd esd protection uart 27mhz IC USB datasheet abstract |
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| Abstract: product development cost Multiple clock input frequencies supported Allows USB PHY to operate from the system clock, eliminating the need for any external crystal oscillator for the USB PHY Ability , Solution! Ext. Reg. Hi-Speed USB PHY DP SMSC SOLUTION USB PHY USB Switch DP ULPI Signals to Controller DM DM OSC SPI Signals to Processor Control Full-Speed USB PHY , Oscillator USB Connector External VBus OVP IC VBus OVP DM Full-Speed USB PHY or Power ... | Original |
2 pages, |
USB332X usb phy 27mhz IC USB datasheet abstract |
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| Abstract: VCNT1 O 80 VDDXT P /USB PHY 1.5V 81 VSSXT P /USB PHY 82 XIN1 I X /USB PHY 83 XOUT1 B X /USB PHY 84 VDDRTC P RTC 85 VSSRTC , (RTC or LSI ) 91 AVDDPHY1 P USB PHY 1.5V 92 AVSSPHY1 P USB PHY 93 AVSSPHY1 P USB PHY 94 RREF B 95 AVSSPHY2 P USB PHY 96 AVDDPHY2 P USB PHY 3.3V 97 AVDDPHY2 P USB PHY 3.3V 98 AVSSPHY2 P USB PHY 99 ... | Original |
24 pages, |
VDDRTC TQFP120 A1696 16CV33BS 14X14 RTC p1F LC823410 datasheet abstract |
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| Abstract: 1 I î I (è(è fi \ IH Li-Ion Security TS ADC USR Host 2.0 USB OTG 2.0 TFT LCD controller RGB/CPU MIPI l/F Main TFT LCD &TSP 1/2/4/8/16/24 bpp UptoWVGA USB PHY USB PHY Hi |st De SPI 2x & TS l/F SD/MMC 3x HS-MMC SDHC USB modem or USB HDD ActiveSync, Debug Mobile TV: ATSC-MH/CMMB/DVB-T HD Radio eMMC4.4 ... | OCR Scan |
2 pages, |
S5P6450 S5P6450 abstract |
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| Abstract: the i.MX31 USB PHY by Multimedia Applications Division Freescale Semiconductor, Inc. Austin, TX , the i.MX31 USB PHY, Rev. 0 2 Freescale Semiconductor Booting Figure 1 shows the ISP 1301 serial interface. Figure 1. ISP 1301 Serial Interface Changing the i.MX31 USB PHY, Rev. 0 , USB PHY, Rev. 0 4 Freescale Semiconductor Booting Figure 4 and Figure 5 show two , shows the USB3317 USB3317 host interface. Figure 4. USB3317 USB3317 Host Interface Changing the i.MX31 USB PHY ... | Original |
12 pages, |
USB3311 usb phy AN4130 USB3317 AN4130 abstract |
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| Abstract: Diagram JTAG USB TAP Controller USB 2.0 Hub Upstream USB PHY EEPROM Controller Downstream USB PHY Downstream USB PHY* USB USB Ethernet Downstream USB PHY* USB SMSC Literature #NP-ETH-086-11/09-1 NP-ETH-086-11/09-1 Downstream USB PHY EEPROM (Optional) Ethernet PHY 10/100 , LAN951x Family Industry's First Single-Chip, Hi-Speed USB 2.0 Hub and High-Performance 10/100 Ethernet Controllers SMSC's LAN951x is the industry's first family of fully-integrated, Hi-Speed USB 2.0 ... | Original |
2 pages, |
LAN9513 usb 2.0 hub HDMI to ethernet chip hub ethernet tap LAN9514 LAN9512 DIAGRAM plasma TV usb video player circuit diagram LAN951x PCI express PCB footprint usb phy ethernet to usb HDMI to ethernet LAN9512 abstract |
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| Abstract: . 1 USB PHY Layout Guide , . Power Supply and Clock Connection to the USB PHY . USB , Documentation Feedback USB 2.0 Board Design and Layout Guidelines 1 www.ti.com USB PHY Layout Guide 2 USB PHY Layout Guide The following sections describe in detail the specific guidelines for USB , guidelines when laying out a new design for the USB physical layer (PHY). These guidelines help minimize ... | Original |
11 pages, |
high speed parallel to usb IC connector datasheet abstract |
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| Abstract: Four integrated downstream USB 2.0 PHYs - One integrated upstream USB 2.0 PHY Integrated 10/100 , : Programmable USB diff-pair pin location - PHY Boost: Programmable USB signal drive strength - Select , 2.0 hub, four integrated downstream USB 2.0 PHYs, an integrated upstream USB 2.0 PHY, a 10/100 , LAN9514/LAN9514i JTAG USB DP/DM TAP Controller Upstream USB PHY Downstream USB PHY USB DP/DM 10/100 Ethernet Controller USB 2.0 Hub Downstream USB PHY Downstream USB PHY ... | Original |
5 pages, |
usb phy LAN9514i IEC61249-2-21 hub ethernet tap LAN9514-JZX Hp notebook ethernet lan9514 LAN9514 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| , falling edge trigger. */ PMU_Init(); /* Put X/Y/Z into sleep mode. */ /* For LPC11xx, USB_PLL and USB_PHY bits should not be touched as they don't exist in the current silicon. Depending on the configuration, these bits need to be carefully selected. */ // regVal = USB_PHY_PD|USB_PLL /* * $Id: pmutest.c 3635 2010-06-02 00:31:46Z usb00423 $ * Project: NXP LPC11xx PMU (Power www.datasheetarchive.com/download/2949375-595946ZC/code.bundle.lpc11xx.keil.zip (pmutest.c) |
NXP | 25/09/2010 | 304.71 Kb | ZIP | code.bundle.lpc11xx.keil.zip |
| _PLL_PD (0x1 /* * $Id: pmu.h 3632 2010-06-01 22:54:42Z usb00423 $ * Project: NXP LPC13xx PMU example * * Description: * This file contains PMU code header definition. * * * Software that is described herein is for illustrative purposes only * which provides customers with www.datasheetarchive.com/download/39581382-595947ZC/code.bundle.lpc13xx.keil.zip (pmu.h) |
NXP | 08/06/2011 | 1045.36 Kb | ZIP | code.bundle.lpc13xx.keil.zip |
| _PLL_PD (0x1 /* * $Id: pmu.h 3635 2010-06-02 00:31:46Z usb00423 $ * Project: NXP LPC11xx PMU example * * Description: * This file contains PMU code header definition. * * * Software that is described herein is for illustrative purposes only * which provides customers with www.datasheetarchive.com/download/2949375-595946ZC/code.bundle.lpc11xx.keil.zip (pmu.h) |
NXP | 25/09/2010 | 304.71 Kb | ZIP | code.bundle.lpc11xx.keil.zip |
| _OSC_PD (0x1 www.datasheetarchive.com/download/39581382-595947ZC/code.bundle.lpc13xx.keil.zip (pmu.h.svn-base) |
NXP | 08/06/2011 | 1045.36 Kb | ZIP | code.bundle.lpc13xx.keil.zip |
| ) /* USB clock is used */ LPC_SYSCON->PDRUNCFG &= ~(1 */ LPC_SYSCON->PDRUNCFG |= (1 . // 0 = is disabled // // // // USB PLL Control Register => P = 8 // // // USB PLL Clock Source Select Register (USBPLLCLKSEL) // SEL: USB PLL Clock Source // USB PLL clock source must be switched to System www.datasheetarchive.com/download/40219045-595945ZC/code.bundle.lpc11uxx.keil.zip (system_LPC11Uxx.c) |
NXP | 11/04/2011 | 218.62 Kb | ZIP | code.bundle.lpc11uxx.keil.zip |
| ) /* USB clock is used */ LPC_SYSCON->PDRUNCFG &= ~(1 */ LPC_SYSCON->PDRUNCFG |= (1 > // // USB PLL Control Register (USBPLLCTRL) // F_clkout = M * F_clkin = F => P = 4 // P = 8 // // // USB PLL Clock Source Select Register (USBPLLCLKSEL) // SEL: USB PLL Clock Source // USB PLL clock source must www.datasheetarchive.com/download/39581382-595947ZC/code.bundle.lpc13xx.keil.zip (system_LPC13xx.c.svn-base) |
NXP | 08/06/2011 | 1045.36 Kb | ZIP | code.bundle.lpc13xx.keil.zip |
| */ LPC_SYSCON->PDRUNCFG &= ~(1 */ LPC_SYSCON->PDRUNCFG |= (1 . // 0 = is disabled // // // // USB PLL Control Register => P = 8 // // // USB PLL Clock Source Select Register (USBPLLCLKSEL) // SEL: USB PLL Clock Source // USB PLL clock source must be switched to System www.datasheetarchive.com/download/39581382-595947ZC/code.bundle.lpc13xx.keil.zip (system_LPC13xx.c) |
NXP | 08/06/2011 | 1045.36 Kb | ZIP | code.bundle.lpc13xx.keil.zip |
| Off-the-shelf boards Available from Gleichmann USB Phy interface 2 Channel Gigabit Ethernet USB, Ethernet, DVI, SD/MMC, FlexRay, CAN User expandable Third-party IP and peripherals FPGA RTL, netlists, and images Development Tools Keil MDK-ARM (evaluation version) ULINK2 USB & Examples 5 MPS Block Diagram BaseBoard ProcessorBoard DUT FPGACPU FPGA NOR SSRAMSSRAM DDR USB Video SMBSMB Ethernet USB Host USB Device/OTG DVI-A AC97 D/A, A/D CAN/LIN, FlexRay, & RS232 RS232 RS232 RS232 Child board expansion www.datasheetarchive.com/download/66603255-30108ZC/cortex-m_workshop_tour.zip (MPS 06-2009.pdf) |
ARM | 29/06/2009 | 11820.25 Kb | ZIP | cortex-m_workshop_tour.zip |
| 10Mbps Ethernet networking. This dual PHY layer functionality enables a device such as a USB integrating AMDs HomePHY device into our USB Phoneline Adapter, Peracom delivers an easily installable USB PCs in the house by attaching outside the PC via USB." About HomePHY The HomePHY Appliances- SUNNYVALE, CA - APRIL 26, 1999 - AMD today announced the HomePHY(TM) device, a single chip -endorsed Home Phoneline Networking Alliance (HomePNA) technology into their products. AMDs HomePHY device www.datasheetarchive.com/files/amd/docs/wcd00004/wcd004cf.htm |
AMD | 29/04/1999 | 8.29 Kb | HTM | wcd004cf.htm |
| AMD - Am79C901 Am79C901 HomePHY(TM) Am79C901 Am79C901 HomePHY Single Chip 1/10 Mbps Home Networking PHY The Am79C901 Am79C901 HomePHY is a single-chip device that contains both a physical layer (PHY) for 1 HomePHY has two interfaces, General Purpose Serial Interface (GPSI) and Media Independent telephone (POTS) service. The built-in Ethernet transceiver is a PHY device supporting the IEEE www.datasheetarchive.com/files/amd/docs/wcd00004/wcd004d0.htm |
AMD | 29/04/1999 | 7.99 Kb | HTM | wcd004d0.htm |