NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS

Datasheet Archive - Datasheet Search Engine

 

ttl 7476 datasheets

Catalog Datasheet Results Type PDF Document Tags
Abstract: Digital Integrateci Circuits TTL Flip-Flops A range of standard '7400 series' TTL flip-flops is available in plastic dual-in-line encapsulation. DIC 7470 D.C.CIocked J-K Flip-Flop DIC 7472 J-K Master-Slave Flip-Flop DIC 7473 DUAL J-K Master-Slave Flip-Flop DIC 7474 DUAL D type Edge-Triggered Flip-Flop DIC 7476 DUAL J-K Master-Slave Flip-Flop with Preset and Clear DIC 7470 DIC 7472 DIC7473 DIC7473 DIC 7474 PRESET 2 [j CLEAR 7 1 8 DIC 7476 TO 116 14 LEAD MAX 5 08 HH -pi |4-8-9- •1C UH c £ MAX I ... OCR Scan
datasheet

1 pages,
35.71 Kb

TTL 7472 jk 7474 7474 7472 ttl 7474 flip flops 7470 TTL Jk 7476 7474 ttl 7474 J-K Flip-Flop TTL 7476 Flip-Flop 7476 7473 dual JK 7476 7474 D flip-flop datasheet abstract
datasheet frame
Abstract: FAIRCHILD TTL/SSI . 9N76/5476 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks. Inputs to the master section are controlled by the clock , FAIRCHILD TTL/SSI • 9N76/5476 9N76/5476, 7476 RECOMMENDED OPERATING CONDITIONS PARAMETER 9N76XM/5476XM 9N76XM/5476XM 9N76XC/7476XC 9N76XC/7476XC , -57 mA 9N76/7476 'CC Supply Current 20 40 mA Vcc = MU- 49 SWITCHING CHARACTERISTICS (TA = 25°C ... OCR Scan
datasheet

2 pages,
116.44 Kb

7476 master slave 7476 N connection 7476 fairchild Diagram of 7476 ic 7476 ttl Flip-Flop 7476 ttl 7476 of ic 7476 IC 7476 JK 7476 VCC input 7476 Connection diagram circuit diagram with IC 7476 logic ic 7476 9N76/5476 9N76/5476 abstract
datasheet frame
Abstract: Sjgnetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , , forcing the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 74LS76 TYPICAL f , 5-114 853-0566 81501 Signetics Logic Products Product S pecification Flip-Flops 7476 , the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable while the Clock ... OCR Scan
datasheet

6 pages,
145.77 Kb

TTL 74ls76 7476 logic diagram LS 74LS76 Flip-Flop 7476 7476 ttl 74LS76 logic diagram Diagram of 7476 7476 Pin Configuration of 7476 J-K Flip-Flop 7476 74LS76 7476 PIN DIAGRAM input and output 7476 pin configuration datasheet abstract
datasheet frame
Abstract: Flip-Flops 7476, LS76 TEST CIRCUITS AND WAVEFORMS VM = 1.3V for 74LS; V m = 1-5V for all other TTL , Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is , the outputs to the steady state levels as shown in the Function Table. TYPE 7476 74LS76 74LS76 TYPICAL f MAx , 81501 Signetics Logic Products Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM ... OCR Scan
datasheet

6 pages,
251.41 Kb

TTL 7476 PIN CONFIGURATION 7476 7476 ttl 7476 pin configuration 7476 J-K Flip-Flop Jk 74ls76 pin out 7476 PIN DIAGRAM input and output pin diagram of 7476 74LS76 datasheet abstract
datasheet frame
Abstract: , Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master , and Data inputs, forcing the outputs to the steady state levels as shown in the Function Table. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , Signetics Logic Products _Product Specificotion Flip-Flops 7476, LS76 LOGIC DIAGRAM cp ldoz800s , to the negative edge of the Clock for predictable operation. 3. The J and K inputs of the 7476 must ... OCR Scan
datasheet

6 pages,
139.61 Kb

74ls76 j_k TTL 7476 74ls76 Jk 7476 i c 74ls76 ci 74ls76 LS 7476 PIN CONFIGURATION 7476 7476 pin configuration 7476 J-K Flip-Flop 7476 TTL 74ls76 7476 PIN DIAGRAM input and output 7476 ttl datasheet abstract
datasheet frame
Abstract: , Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master , -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 74LS76 , Manufacturer Signetics Logic Products _Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM ld02900s , negative edge of the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable ... OCR Scan
datasheet

6 pages,
146.88 Kb

N7476N LS76 pin diagram for jk flip flop 7476 N74LS76N 74LS76 ttl 7476 pin configuration 74LS76 Jk 7476 TTL 7476 J-K Flip-Flop 7476 PIN CONFIGURATION 7476 7476 J-K Flip-Flop pin diagram of ttl 7476 datasheet abstract
datasheet frame
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 54LS/74LS76 2 7 , 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS Item Function DEVICE NO. Inputs , Dual JK 54LS/74LS113 54LS/74LS113 J, K ~L X - 60 12 20 D63 3I, 6A, 9A 21 Dual JK 54/7476 J, K J L X X 20 25 100 D58 ... OCR Scan
datasheet

2 pages,
66.76 Kb

flip flop jk D-59B 7476 ttl 7473 dual JK 74LS73 JK 7472 PIN DIAGRAM 74LS74 TTL 7474 16 PIN 7476 PIN DIAGRAM 74LS73 dual JK 7474 PIN DIAGRAM TTL 7474 jk 7474 7476 JK datasheet abstract
datasheet frame
Abstract: TEXAS 75 26 5 TTL SN 5476, SN 7476 DUAL J-K FLIP FLOPS WITH PRESET AND CLEAR logic diagrams (positive logic) TTL D e v ic e s 2 248 INSTTOJMENTS POST OFPICE BOX 6 5 5 0 1 2 · D ALLAS. TEXAS 75 26 5 SN 5476, SN 54LS 76A , SN 7476, S N 74 LS7 6A DUAL J K FLIP FLOPS WITH PRESET AND CLEAR , Te x a s ^ In s t r u m e n t s POST OFFICE BOX 6 5 5 0 1 2 · D ALLAS . TEXAS 75 26 5 249 TTL D e v ic e s logic sym bols* SN 5476, SN 54LS76A 54LS76A , SN 7476, SN 74 LS 7 6A DUAL J-K FLIP-FLOPS ... OCR Scan
datasheet

6 pages,
117.03 Kb

logic diagram of ic 7476 ic 7476 IC 7476 JK 7476 ic specifications SN547G SN54LS76A SN7476 SN74LS76A SN547G abstract
datasheet frame
Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd D60 9024, 54/74109, 54S/74S109 54S/74S109, 54LS/74LS109 54LS/74LS109 5 11 ~LT 2 - J SD 0 _6 14 0 4 - CP 12 CP 3-0 K Co Q »1 13 -0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd "O 11 J_ , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 54LS/74LS76 2 7 ... OCR Scan
datasheet

1 pages,
24.26 Kb

74S109 CD-D60 Fairchild 902 Fairchild 9020 TTL 74109 ttl 7474 14 PIN 7476 master slave 7474 16 PIN 74LS109 74LS73 74LS107 74ls74 TTL 74ls76 74ls76 54S/74S109 54LS/74LS109 54S/74S109 abstract
datasheet frame
Abstract: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and , UK ). Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together. The following tables are available . TTL Device Summary CMOS Device , device is suitable for your purposes. 1 of 12 E&OE. TTL Device Summary Please click on a , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2-Input ... Original
datasheet

12 pages,
125.46 Kb

74138 Decoder 7404 ttl inverter 74241 4070 CMOS XOR 7476 counter 74374 4001 4011 cmos 74244 7476 J-K Flip-Flop 7493 flip-flop counter design a BCD counter using j-k flipflop 7408, 7404, 7486, 7432 74373 cmos dual s-r latch datasheet abstract
datasheet frame

Datasheet Content (non pdf)

Abstract Saved from Date Saved File Size Type Download
Over 1.1 million files (1986-2014): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
* * * *SRC=7476;7476;TTL;74xx;J-K Flip-Flop *SYM=T7476 T7476 T7476 T7476 *7476 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR * * * STANDARD TTL DIGITAL LIBRARY BASED ON THE TEXAS * * INSTRUMENTS DATA BOOK (Volume 1 * * * * * *SRC=7400;7400;TTL;74xx;2 input NAND gate *SYM=NAND2 *7400 QUADRUPLE 2-INPUT POSITIVE-NAND GATES * * * *SRC=7402;7402;TTL;74xx;2 input NOR gate *SYM=NOR2 *7402 QUADRUPLE 2-INPUT POSITIVE-NOR GATES * * * *SRC=7404;7404;TTL;74xx;inverter *SYM=INV *7404 HEX INVERTERS * .subckt 7404 in out *FAMILY TTLin
www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/7400.lib
Spice Models 18/04/2010 72.32 Kb LIB 7400.lib
* Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2-7 * bss 2/2/94 * * * - 7401 - * Quad 2-Input Nand Gates With Open-Collector Outputs * * The TTL Logic Data Book 7402 - * Quad 2-Input Nor Gates * * The TTL Logic Data Book, 1988, TI Pages 2-13 to 2-17 * * * - 7403 - * Quad 2-Input Nand Gates With Open-Collector Outputs * * The TTL Logic Data Book 7404 - * Hex Inverters * * The TTL Logic Data Book, 1988, TI Pages 2-25 to 2-29 * bss 2
www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/digdemo.lib
Spice Models 18/04/2010 128.15 Kb LIB digdemo.lib
ive-And Gates * 74S11 74S11 74S11 74S11 S-series TTL Triple 3-input Positive-AND gates * clock4-bit bistable latches ) * 7476 Dual J-K Flip-Flops with Preset and Clear * *- * * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names .subckt 7401 Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names
www.datasheetarchive.com/files/spicemodels/misc/eval.lib
Spice Models 20/12/2001 295.35 Kb LIB eval.lib
* Library of Standard 74 TTL Family Digital Models * * Copyright Cadence Design Systems, Inc. * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23 Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 *- * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2
www.datasheetarchive.com/files/spicemodels/misc/7400.lib
Spice Models 19/12/2001 282.17 Kb LIB 7400.lib
* Library of Standard 74 TTL Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights *- * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update *- * 7403 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL
www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/7400.lib
Spice Models 29/07/2012 282.15 Kb LIB 7400.lib
- * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2-7 * bss 2 * -74ALS00- -74ALS00- -74ALS00- -74ALS00- * Quadruple 2-Input Positive NAND Gate * Motorola Schottky TTL Data Book,1983, pages 5-2 to 2-Input Nand Gate * * NS FAST Advanced Schottky TTL Data Book, 1988 * jds 2-2-94 Pages 4-6 to * * * - 74H00 74H00 74H00 74H00 - * Quad 2-Input Nand Gates * * The TTL Data Book, Vol. 2, 1985, TI Pages 3-3 to * - 74LS00 74LS00 74LS00 74LS00 - * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to
www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/dig000.lib
Spice Models 18/04/2010 473.91 Kb LIB dig000.lib
* Digital Library: 74AC652 74AC652 74AC652 74AC652 to *-74AC652- -74AC652- -74AC652- -74AC652- * Octal Bus Transceiver and Register with 3-State Outputs * TI Advanced CMOS Logic Data Book, 1993, pages 2-541 to 2-548 * jat 12/28/95 .SUBCKT 74AC652 74AC652 74AC652 74AC652 + OEAB OEBABAR CLKBA CLKAB SBA SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 LOGICEXP(36,18) DPWR DGND + SBA SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B
www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/dig652.lib
Spice Models 18/04/2010 549.9 Kb LIB dig652.lib
No abstract text available
www.datasheetarchive.com/download/89854025-739697ZC/20429-v1.pl
SGS-Thomson 12/05/1995 272.67 Kb PL 20429-v1.pl
No abstract text available
www.datasheetarchive.com/download/7883722-739696ZC/20429.pl
SGS-Thomson 07/08/1995 272.68 Kb PL 20429.pl
No abstract text available
www.datasheetarchive.com/download/99994695-739555ZC/20350.pl
SGS-Thomson 07/08/1995 331.93 Kb PL 20350.pl