NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Digital Integrateci Circuits TTL Flip-Flops A range of standard '7400 series' TTL flip-flops is available in plastic dual-in-line encapsulation. DIC 7470 D.C.CIocked J-K Flip-Flop DIC 7472 J-K Master-Slave Flip-Flop DIC 7473 DUAL J-K Master-Slave Flip-Flop DIC 7474 DUAL D type Edge-Triggered Flip-Flop DIC 7476 DUAL J-K Master-Slave Flip-Flop with Preset and Clear DIC 7470 DIC 7472 DIC7473 DIC7473 DIC 7474 PRESET 2 [j CLEAR 7 1 8 DIC 7476 TO 116 14 LEAD MAX 5 08 HH -pi |4-8-9- •1C UH c £ MAX I ... | OCR Scan |
1 pages, |
7474 D flip flop 7472 7474 jk 7474 7470 TTL 7474 flip flops 7474 J-K Flip-Flop Jk 7476 7474 ttl TTL 7476 7473 dual JK Flip-Flop 7476 Flip-Flop 7470 7472 Flip-Flop DIC7473 DIC7473 abstract |
|
|||
| Abstract: FAIRCHILD TTL/SSI . 9N76/5476 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks. Inputs to the master section are controlled by the clock , FAIRCHILD TTL/SSI • 9N76/5476 9N76/5476, 7476 RECOMMENDED OPERATING CONDITIONS PARAMETER 9N76XM/5476XM 9N76XM/5476XM 9N76XC/7476XC 9N76XC/7476XC , -57 mA 9N76/7476 'CC Supply Current 20 40 mA Vcc = MU- 49 SWITCHING CHARACTERISTICS (TA = 25°C ... | OCR Scan |
2 pages, |
7476 JK ic 7476 ttl 7476 Connection diagram 9N76 7476 J-K Flip-Flop 7476 fairchild IC 7476 JK 7476 master slave circuit diagram with IC 7476 ttl 7476 Flip-Flop 7476 7476 VCC input of ic 7476 9N76/5476 9N76/5476 9N76/5476 abstract |
|
|||
| Abstract: , Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master , and Data inputs, forcing the outputs to the steady state levels as shown in the Function Table. 7476 , (TOTAL) 7476 20MHz 10mA 74LS76 74LS76 45MHz 4mA ORDERING CODE PACKAGES COMMERCIAL RANGE VCC = 5V±5%; TA = , Signetics Logic Products _Product Specificotion Flip-Flops 7476, LS76 LOGIC DIAGRAM cp ldoz800s , to the negative edge of the Clock for predictable operation. 3. The J and K inputs of the 7476 must ... | OCR Scan |
6 pages, |
TTL 7476 7476 logic diagram Flip-Flop 7476 ci 74ls76 74ls76 Jk 7476 PIN CONFIGURATION 7476 i c 74ls76 7476 pin configuration 7476 J-K Flip-Flop 7476 TTL 74ls76 7476 ttl 74LS76 74LS76 abstract |
|
|||
| Abstract: , Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master , -1.6mA l,L. and a 74LS unit load (LSul) is 20juA l)H and -0.4mA l|L. 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 7476 20MHz 10mA 74LS76 74LS76 , Manufacturer Signetics Logic Products _Product Specification Flip-Flops 7476, LS76 LOGIC DIAGRAM ld02900s , negative edge of the Clock for predictable operation. 3. The J and K inputs of the 7476 must be stable ... | OCR Scan |
6 pages, |
LS76 N7476N pin diagram for jk flip flop 7476 PIN CONFIGURATION 7476 N74LS76N Jk 7476 TTL 7476 74LS76 ttl 74LS76 7476 pin configuration J-K Flip-Flop 7476 7476 J-K Flip-Flop pin diagram of ttl 7476 74LS76 abstract |
|
|||
| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 54LS/74LS76 2 7 , 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS Item Function DEVICE NO. Inputs , Dual JK 54LS/74LS113 54LS/74LS113 J, K ~L X - 60 12 20 D63 3I, 6A, 9A 21 Dual JK 54/7476 J, K J L X X 20 25 100 D58 ... | OCR Scan |
2 pages, |
7474 PIN DIAGRAM pin diagram 7474 ttl 74ls109 TTL 74107 flip flop jk pin diagram of 7473 Jk 74ls76 7476 ttl 7473 dual JK TTL 7474 7476 PIN DIAGRAM jk 7474 74LS74 TTL datasheet abstract |
|
|||
| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd D60 9024, 54/74109, 54S/74S109 54S/74S109, 54LS/74LS109 54LS/74LS109 5 11 ~LT 2 - J SD 0 _6 14 0 4 - CP 12 CP 3-0 K Co Q »1 13 -0 K Cd 0 Vcc = Pin 16 GND = Pin 8 D56 9022 SD J Q CP K 0 Cd "O 11 J_ , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 54LS/74LS76 2 7 ... | OCR Scan |
1 pages, |
74S109 ttl 7474 14 PIN Fairchild 9020 Fairchild 902 CD-D60 74LS109 74LS73 74LS107 74ls74 TTL 74ls76 7476 ttl 7474 14 PIN 74ls76 ttl 74ls109 datasheet abstract |
|
|||
| Abstract: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and , UK ). Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together. The following tables are available . TTL Device Summary CMOS Device , device is suitable for your purposes. 1 of 12 E&OE. TTL Device Summary Please click on a , 7476 7483 7485 7486 7490 7493 74121 2 of 12 Function Quad 2-Input NAND Gate Quad 2-Input ... | Original |
12 pages, |
decoder 7448 74373 74138 Decoder 74241 7493 flip-flop counter 74244 4070 CMOS XOR 7476 counter 4001 4011 cmos 74374 7476 J-K Flip-Flop 7408, 7404, 7486, 7432 74373 cmos dual s-r latch latch 74574 datasheet abstract |
|
|||
| Abstract: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED ill (9 D UJ (3 Z o (3 in > O a z o in o z < X o I-3 a. I- O D55 9020 J Q CP K „ 0 Cd D60 9024, 54/74109, 54S/74S109 54S/74S109, 54LS/74LS109 54LS/74LS109 5 11 ~LT 2 - J SD 0 _6 14 0 4 - CP 12 CP 3-0 K , 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 54H/74H103 D58 54/7476, 54H/74H76 54H/74H76, 54LS/74LS76 54LS/74LS76 2 7 , 13 13-49 FAIRCHILD DIGITAL TTL TTL SINGLE AND DUAL FLIP-FLOPS (Cont'd) Item Function DEVICE ... | OCR Scan |
2 pages, |
74LS73 dual JK 74ls76 74196 74LS76 FAIRCHILD ttl 74ls109 TTL 74109 ttl 74107 pin diagram of 7473 7473 latch 74ls74 74LS109 74ls107 ci 74LS74 fairchild 9024 datasheet abstract |
|
|||
| Abstract: 512x9 ROM for general purpose use. This device has TTL compatible inputs and outputs and requires +5V , TYPICAL ACCESS TIME • STATIC OPERATION • OUTPUT LATCHES • TTL/DTL COMPATIBLE INPUTS • TTL/DTL , can be driven directly by standard bipolar integrated circuits (TTL, DTL, etc.). The data output buffers are capable of sinking a minimum of 1.6mA to drive one standard TTL load. STANDARD CODES The , next column to right. 2. Undefined addresses result in all outputs going low (TTL "0"). 3. Black ... | OCR Scan |
7 pages, |
CHARACTER table application pin diagram decoder 7476 CM3400 7476 truth table 7x9 decoder 7476 ttl 7476 PIN DIAGRAM 2526N PIN CONFIGURATION 7476 pin diagram of ttl 7476 datasheet abstract |
|
|||
| Abstract: TTL. SAMSUNG gate array design activity is performed on the computer aided design system which , (famout: 2) • Maximum Toggling Frequency: 40MHz • High density 3.5 micron geometries • TTL and CMOS I/O , Respective Manufacturer 177 KG10000 KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY EQUIVALENT CELL COUNTS OF LS TTL TTL Pari No. Count TTL Part No. Count TTL Part No. Count TTL Part No. Count 7400 4 7470 16 74152 24 , 74259 48 7404 4 7474 15 74156 21 74260 6 7405 4 7475 14 74157 22 74261 58 7406 3 7476 20 74158 23 ... | OCR Scan |
6 pages, |
74274 74266 74284 74144 74259 7408, 7404, 7486, 7432 4001 4011 cmos 74226 ttl 74395 74381 LS 74141 7404 7408 7432 ttl 74183 CMOS 4017 series KG10000 KG10000 KG10000 abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| * * * *SRC=7476;7476;TTL;74xx;J-K Flip-Flop *SYM=T7476 *7476 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR * * * STANDARD TTL DIGITAL LIBRARY BASED ON THE TEXAS * * INSTRUMENTS DATA BOOK (Volume 1 * * * * * *SRC=7400;7400;TTL;74xx;2 input NAND gate *SYM=NAND2 *7400 QUADRUPLE 2-INPUT POSITIVE-NAND GATES * * * *SRC=7402;7402;TTL;74xx;2 input NOR gate *SYM=NOR2 *7402 QUADRUPLE 2-INPUT POSITIVE-NOR GATES * * * *SRC=7404;7404;TTL;74xx;inverter *SYM=INV *7404 HEX INVERTERS * .subckt 7404 in out *FAMILY www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/7400.lib |
Spice Models | 18/04/2010 | 72.32 Kb | LIB | 7400.lib |
| * * * - 7476 - * Dual J-K Flip-Flops With Preset And Clear * * The TTL Logic Data Book, 1988, TI - * Quad 2-Input Nand Gates * * The TTL Logic Data Book, 1988, TI Pages 2-3 to 2-7 * bss 2 * * * - 7401 - * Quad 2-Input Nand Gates With Open-Collector Outputs * * The TTL Logic Data Book * * * - 7402 - * Quad 2-Input Nor Gates * * The TTL Logic Data Book, 1988, TI Pages 2-13 to 2 * * * - 7403 - * Quad 2-Input Nand Gates With Open-Collector Outputs * * The TTL Logic Data Book www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/digdemo.lib |
Spice Models | 18/04/2010 | 128.15 Kb | LIB | digdemo.lib |
| * * * *SRC=5476;5476;TTL;54xx;J-K Flip-Flop *SYM=T7476 *5476 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR * * * STANDARD TTL DIGITAL LIBRARY BASED ON THE TEXAS * * INSTRUMENTS DATA BOOK (Volume 1 * * * * * *SRC=54152A;54152A;TTL;54xx;2 input NAND *SYM=T54152A T54152A T54152A T54152A *54152A MULTIPLEXER/DATA SELECTOR 8-1 LINE ;5400;TTL;54xx;2 input NAND gate *SYM=NAND2 *5400 QUADRUPLE 2-INPUT POSITIVE-NAND GATES * .subckt 5400 * * * *SRC=5402;5402;TTL;54xx;2 input NOR gate *SYM=NOR2 *5402 QUADRUPLE 2-INPUT POSITIVE-NOR GATES www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/5400.lib |
Spice Models | 18/04/2010 | 67.42 Kb | LIB | 5400.lib |
| * * * *SRC=54LS76A 54LS76A 54LS76A 54LS76A;54LS76A 54LS76A 54LS76A 54LS76A;TTL;54LSxx;J-K Flip-Flop *SYM=T7476 *54LS76A 54LS76A 54LS76A 54LS76A DUAL J-K FLIP-FLOPS WITH PRESET * * * * * *SRC=54LS00 54LS00 54LS00 54LS00;54LS00 54LS00 54LS00 54LS00;TTL;54LSxx;2 input NAND gate *SYM=NAND2 *54LS00 54LS00 54LS00 54LS00 QUADRUPLE 2-INPUT POSITIVE ) .ends * * * *SRC=54LS01 54LS01 54LS01 54LS01;54LS01 54LS01 54LS01 54LS01;TTL;54LSxx;2 input NAND gate *SYM=NAND2 *54LS =54LS02 54LS02 54LS02 54LS02;54LS02 54LS02 54LS02 54LS02;TTL;54LSxx;2 input NOR gate *SYM=NOR2 *54LS02 54LS02 54LS02 54LS02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES * * * *SRC=54LS03 54LS03 54LS03 54LS03;54LS03 54LS03 54LS03 54LS03;TTL;54LSxx;2 input NAND gate *SYM=NAND2 *54LS03 54LS03 54LS03 54LS03 QUADRUPLE 2-INPUT POSITIVE www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/54ls.lib |
Spice Models | 18/04/2010 | 59.29 Kb | LIB | 54ls.lib |
| * * * * * *SRC=74LS00 74LS00 74LS00 74LS00;74LS00 74LS00 74LS00 74LS00;TTL;74LSxx;2 input NAND gate *SYM=NAND2 *74LS00 74LS00 74LS00 74LS00 QUADRUPLE 2-INPUT POSITIVE ;74LS01 74LS01 74LS01 74LS01;TTL;74LSxx;2 input NAND gate *SYM=NAND2 *74LS01 74LS01 74LS01 74LS01 QUADRUPLE 2-INPUT POSITIVE-NAND GATES *WITH ;74LS02 74LS02 74LS02 74LS02;TTL;74LSxx;2 input NOR gate *SYM=NOR2 *74LS02 74LS02 74LS02 74LS02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES _nor(rise_delay=10n fall_delay=10n) .ends * * * *SRC=74LS03 74LS03 74LS03 74LS03;74LS03 74LS03 74LS03 74LS03;TTL;74LSxx;2 input NAND p) .ends * * * *SRC=74LS04 74LS04 74LS04 74LS04;74LS04 74LS04 74LS04 74LS04;TTL;74LSxx;inverter *SYM=INV *74LS04 74LS04 74LS04 74LS04 www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/74ls.lib |
Spice Models | 18/04/2010 | 63.91 Kb | LIB | 74ls.lib |
| + ) *$ *- * 7476 Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 * Library of Standard 74 TTL Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights :32:32 $ * * *$ *- * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2 + ) *$ *- * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/7400.lib |
Spice Models | 29/07/2012 | 282.15 Kb | LIB | 7400.lib |
| + ) *$ *- * 7476 Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 * Library of Standard 74 TTL Family Digital Models * * Copyright Cadence Design Systems, Inc :26:32 $ * * *$ *- * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *$ *- * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2 + ) *$ *- * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 www.datasheetarchive.com/files/spicemodels/misc/7400.lib |
Spice Models | 19/12/2001 | 282.17 Kb | LIB | 7400.lib |
| | Contents | TDA7473 TDA7473 TDA7473 TDA7473 - QUAD BTL DRIVER WITH VOLTAGE REGULATOR | Contents | TDA7476 - CAR RADIO SWITCHES | Contents | TDA9102C TDA9102C TDA9102C TDA9102C - H/V PROCESSOR FOR TTL V.D.U. | Contents | TDA9102F TDA9102F TDA9102F TDA9102F - H/V PROCESSOR FOR TTL V.D.U | Contents | TDA9102T TDA9102T TDA9102T TDA9102T - TDA9102C/T TDA9102C/T TDA9102C/T TDA9102C/T H/V PROCESSOR FOR TTL V.D.U | Contents www.datasheetarchive.com/files/stmicroelectronics/stonline/books/pdf/alpha/ds/t-v2.htm |
STMicroelectronics | 14/06/1999 | 197.01 Kb | HTM | t-v2.htm |
| Triple 3-input Posit ive-And Gates * 74S11 74S11 74S11 74S11 S-series TTL Triple 3-input Positive * clock4-bit bistable latches ) * 7476 Dual J-K Flip-Flops with Preset and Clear * *- * * 7400 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06 + ) *- *$ * 7401 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2 =8ns tphlmx=15ns + ) *- *$ * 7402 Quadruple 2-input Positive-Nor Gates * * The TTL www.datasheetarchive.com/files/spicemodels/misc/eval.lib |
Spice Models | 20/12/2001 | 295.35 Kb | LIB | eval.lib |
| EFFECTS | Contents | TDA7473 TDA7473 TDA7473 TDA7473 - QUAD BTL DRIVER WITH VOLTAGE REGULATOR | Contents | TDA7476 TTL V.D.U. | Contents | TDA9102F TDA9102F TDA9102F TDA9102F - H/V PROCESSOR FOR TTL V.D.U | Contents | TDA9102T TDA9102T TDA9102T TDA9102T - TDA9102C/T TDA9102C/T TDA9102C/T TDA9102C/T H/V PROCESSOR FOR TTL V.D.U | Contents | TDA9103 TDA9103 TDA9103 TDA9103 - DEFLECTION PROCESSOR FOR www.datasheetarchive.com/files/stmicroelectronics/stonline/books/pdf/alpha/ds/t-v1.htm |
STMicroelectronics | 07/04/1999 | 280.4 Kb | HTM | t-v1.htm |