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transistor nb2

Catalog Datasheet MFG & Type PDF Document Tags

EEd2820

Abstract: NP1410 3 NS1a x NS1a 4 5 9 x 9 NB1 6 6 8 NB2 NB2 7 H-2 5 NB1 8 , 8 NS1b 7 6 8 NB2 NB2 7 P.20 002-01 / 20100408 / j6355_eco.fm (11 , 3 NS1a x NS1a 4 5 9 x 9 NB1 6 6 8 NB2 NB2 7 H-2 5 NB1 8 , 8 NS1b 7 6 8 NB2 NB2 7 P.20 002-01 / 20100408 / j6355_eco.fm (16 , 11 ND 6 10 6 10 NB2 NV 7 9 7 9 8 M-2 5 11 NB1 8 N
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TDK TRANSFORMER CATALOG

Abstract: TDK TRANSFORMER USED IN - NB 80 E 01 H 3 NS1a x NS1a 4 5 9 x 9 NB1 6 6 8 NB2 NB2 7 H-2 5 NB1 8 , 4 5 NB1 6 8 NS1b 7 6 8 NB2 NB2 7 · Please refer to P.20 for more , 9 x 9 NB1 6 6 8 NB2 NB2 7 H-2 5 NB1 8 1st side 2-output 4 , NS1b 7 6 8 NB2 NB2 7 · Please refer to P.20 for more details about the list of , NS1a x 4 NS1b NS1 5 11 ND 6 10 6 10 NB2 NV 7 9 7 9 8 M
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Transformer e2-76rtf-ns3-0215

Abstract: 78/bsh 13 - n1 flyback NB1 6 8 NB2 6 NB2 7 H-2 5 NB1 8 1st side 2-output 4 7 I-2 14 , 3 NS1a x NS1a 4 x 5 9 9 NB1 8 NS1b 4 5 NB1 6 8 NB2 7 6 NB2 7 Please refer to P.26 for more details about the list of plans for standard windings and , x 9 NB1 6 8 NB2 6 NB2 7 H-2 5 NB1 8 1st side 2-output 4 7 I , 11 3 NS1a x NS1a 4 x 5 9 9 NB1 8 NS1b 4 5 NB1 6 8 NB2 7
TDK
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Sanken STR

Abstract: ECO2017 11 3 3 NS1a x NS1a 4 5 9 x 9 NB1 6 6 8 NB2 NB2 7 H-2 5 , NB1 6 8 NS1b 7 6 8 NB2 NB2 7 P.20 002-01 / 20100408 , NS1a 4 5 9 x 9 NB1 6 6 8 NB2 NB2 7 H-2 5 NB1 8 1 2 4 7 , 7 6 8 NB2 NB2 7 P.20 002-01 / 20100408 / c6355_eco.fm (16/30) ECO24 , 10 NB2 NV 7 9 7 9 8 M-2 5 11 NB1 8 N-2 16 1 15 16
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Sanken STR ECO2017 TDK EER28L ECO2225 EEd2820 ECO2425 ECO20/ ECO22/ ECO24/ 2002/95/EC STBUL/IEC/60950 UL60335-1
Abstract: 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 , CLK_SEL CLK1 NB2 NB1 NB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OEA VDDOA QA0 QA1 GND QB1 QB0 , -Lead TSSOP 6.50mm x 4.40mm x 0.92mm package body G Package Top View NB2:NB0 Pulldown OEB Pullup 3 , , 9, 10 11 12, 16 13 14, 15 17, 18 19 Name VDD NA2, NA1, NA0 CLK0, CLK1 CLK_SEL NB2, NB1, NB0 OEB GN D , VIH VIL Input High Voltage Input Low Voltage CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB CLK0, CLK1 Integrated Device Technology
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ICS87004I-03 200MH ICS87004AGI-03 199707558G

ICS87004AG

Abstract: ICS87004-03 Pulldown 3 CLK_SEL Pulldown CLK0 Pulldown 0 CLK1 Pulldown 1 NB2:NB0 Pulldown , 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 PIN ASSIGNMENT VDD NA2 NA1 NA0 CLK0 CLK_SEL CLK1 NB2 , , CLK1 Input Pulldown 6 CLK_SEL Input Pulldown 8, 9, 10 NB2, NB1, NB0 Input , , CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB Maximum
Integrated Device Technology
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ICS87004-03 ICS87004AG ICS87004AG-03

ICS87004I-03

Abstract: NB2:NB0 Pulldown N Output Divider NA2:NA0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 , CLK_SEL CLK1 NB2 NB1 NB0 QA0 QA1 VDD0A VDD0B 1 2 3 4 5 6 7 8 9 10 20 19 18 , , CLK1 Input Pulldown 6 CLK_SEL Input Pulldown 8, 9, 10 NB2, NB1, NB0 Input , , NA2:NA0, NB2:NB0 OEA, OEB CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB Minimum Typical
Integrated Device Technology
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Abstract: ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 , QA0 VDD NA2 NA1 NA0 CLK0 CLK_SEL CLK1 NB2 NB1 NB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 , -03 QB0 QB1 20-Lead TSSOP 6.50mm x 4.40mm x 0.92mm package body G Package Top View NB2:NB0 , , NA0 CLK0, CLK1 CLK_SEL NB2, NB1, NB0 OEB GND VDDOB QB0, QB1 QA1, QA0 VDDOA Power Input Input Input , Voltage Input Low Voltage CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB CLK0, CLK1, CLK_SEL, NA2:NA0, NB2 Integrated Circuit Systems
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ICS87004AG03 ICS87004AG-03T ICS87004AG-03LF ICS87004AG-03LFT 87004AG-03

ICS87004-03

Abstract: Pulldown 3 CLK_SEL Pulldown CLK0 Pulldown 0 CLK1 Pulldown 1 NB2:NB0 Pulldown , 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 PIN ASSIGNMENT VDD NA2 NA1 NA0 CLK0 CLK_SEL CLK1 NB2 , , CLK1 Input Pulldown 6 CLK_SEL Input Pulldown 8, 9, 10 NB2, NB1, NB0 Input , , NB2:NB0 OEA, OEB CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB Maximum Units 2 VDD +
Integrated Device Technology
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87004BGI-03LFT

Abstract: ICS87004I-03 NB2:NB0 Pulldown N Output Divider NA2:NA0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 , QA1 CLK0 CLK_SEL CLK1 NB2 NB1 NB0 VDD0A VDD0B 1 2 3 4 5 6 7 8 9 10 20 19 , , 10 NB2, NB1, NB0 Input 11 OE B Input 12, 16 GND Power Pulldown , , CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB CLK0, CLK1, CLK_SEL, NA2:NA0, NB2:NB0 OEA, OEB Minimum Typical
Integrated Device Technology
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87004BGI-03LFT 87004BGI-03LF 250MH ICS87004BGI-03

48-PIN

Abstract: ICS843034-01 M3 M4 M5 M6 M7 PIN ASSIGNMENT M8 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 , S_DATA S_CLOCK C nP_LOAD M8:M0 TEST I L NA2:NA0 NB2:NB0 843034AY-01 , 1 CMOS Fout A0 SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S t T0 NB2 , t S PARALLEL LOADING M0:M8, P_DIV, NA0:NA2, NB0:NB2 M, N, P nP_LOAD t S t , Input 4 NB2 Input Description M divider input. Data latched on LOW-to-HIGH trnsition of
Integrated Circuit Systems
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ICS843034-01 48-PIN ICS84332 MS-026 m6 90 v-0 FREQUENCYICS843034-01 ICS3726-02 ICS1493-17 ICS650-40A ICS252
Abstract: CLK_SEL Pullup Pulldown 3 Pulldown CLK0 Pulldown 0 CLK1 Pulldown 1 NB2:NB0 , ÷5 1 0 1 ÷6 1 1 0 ÷8 1 1 1 ÷16 N Output Divider NB2:NB0 0 0 0 ÷1 (default) 0 0 1 ÷2 0 1 0 ÷3 , CLK1 NB2 NB1 NB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OEA , Pulldown Input clock selection. LVCMOS / LVTTL interface levels. See Table 6. 8, 9, 10 NB2, NB1 , :0=NB2:0). Table 4. OEA Function Table OEA Function 0 Bank A outputs are disabled in Integrated Device Technology
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48-PIN

Abstract: ICS84332 M1 M2 M3 M4 M5 NA0 NA1 · 0°C to 70°C ambient operating temperature NA2 NB0 NB1 NB2 , NA2:NA0 NB2:NB0 84334BY CONFIGURATION INTERFACE LOGIC www.icst.com/products , NB2 NB1 NB0 NA2 NA1 NA0 M5 M4 M3 M2 M1 M0 H nP_LOAD t S PARALLEL LOADING M0:M5, NA0:NA2, NB0:NB2 M, N nP_LOAD t S t H Time FIGURE 1 , NB2 Input Description Determines output divider value as defined in Table 3C, Pulldown
Integrated Circuit Systems
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ICS84334 700MH ICS84334BY ICS84334BYT

48-PIN

Abstract: ICS843034-01 nP_LOAD VCO_SEL M0 M1 M2 M3 M4 M5 M6 M7 PIN ASSIGNMENT M8 NB0 NB1 NB2 OE_REF OE_A , TEST I L NA2:NA0 NB2:NB0 843034AY-01 www.icst.com/products/hiperclocks.html 2 REV , 1 CMOS Fout A0 SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S t T0 NB2 , t S PARALLEL LOADING M0:M8, P_DIV, NA0:NA2, NB0:NB2 M, N, P nP_LOAD t S t , Name 1 M8 2, 3 NB0, NB1 Input 4 NB2 Input Description M divider input. Data
Integrated Circuit Systems
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ICS843034AY-01 625MH ICS843034AY-01T ICS843034A01 ICS843034AY-01LF ICS43034A01L ICS843034AY-01LFT
Abstract: Crystal. PIN ASSIGNMENT CLK nCLK nP_LOAD VCO_SEL M0 M1 M2 M3 M4 M5 NA0 NA1 NA2 NB0 NB1 NB2 OE_REF , SEL0 OE_B MR VCCO_REF REF_CLK OE_REF S_LOAD S_DATA S_CLOCK nP_LOAD M5:M0 NA2:NA0 NB2:NB0 , divider CMOS Fout A0 SERIAL LOADING S_CLOCK S_DATA t T1 S T0 NB2 NB1 NB0 NA2 , LOADING M0:M5, NA0:NA2, NB0:NB2 nP_LOAD t S M, N t H Time FIGURE 1. PARALLEL & SERIAL , Name NA2 NB0, NB1 NB2 OE_REF OE_A OE_B VCC nc VEE TEST FOUTA0, nFOUTA0 VCCOA FOUTB0, nFOUTB0 VCCOB Integrated Circuit Systems
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500MH 100KH 84334AY ICS84334AY ICS84334AYT

48-PIN

Abstract: ICS843034-01 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 , C nP_LOAD M8:M0 TEST I L NA2:NA0 NB2:NB0 843034AY-01 www.icst.com/products , 1 CMOS Fout A0 SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S T0 NB2 NB1 , t S PARALLEL LOADING M0:M8, P_DIV, NA0:NA2, NB0:NB2 M, N, P nP_LOAD t S t , Name 1 M8 2, 3 NB0, NB1 Input 4 NB2 Input Description M divider input. Data
Integrated Circuit Systems
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640MH

ICS843034-01

Abstract: ics84303401 M3 M4 M5 M6 M7 PIN ASSIGNMENT M8 NB0 NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 , S_DATA S_CLOCK C nP_LOAD M8:M0 TEST I L NA2:NA0 NB2:NB0 843034AY-01 , 1 CMOS Fout A0 SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S t T0 NB2 , t S PARALLEL LOADING M0:M8, P_DIV, NA0:NA2, NB0:NB2 M, N, P nP_LOAD t S t , Input 4 NB2 Input Description M divider input. Data latched on LOW-to-HIGH trnsition of
Integrated Circuit Systems
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ics84303401

843034

Abstract: 48-PIN NB1 NB2 OE_REF OE_A OE_B VCC NA0 NA1 NA2 VEE REF_CLK output (core/outputs): 3.3V/3.3V · , S_LOAD S_DATA TEST S_CLOCK C nP_LOAD M8:M0 I L NA2:NA0 NB2:NB0 IDT TM / ICSTM , same frequency SERIAL LOADING S_CLOCK S_DATA T1 t S_LOAD S t T0 NB2 NB1 , S PARALLEL LOADING M0:M8, NA0:NA2, NB0:NB2 M, N nP_LOAD t S t H S_LOAD , 4 NB2 Input 5 OE_REF Input 6 OE_A Input 7 OE_B Input 8, 14
Integrated Device Technology
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ICS843034 ICS843034AY 843034 ICS843034AYLF ICS843034AYT ICS843034-02 222MH
Abstract: Crystal. PIN ASSIGNMENT CLK nCLK nP_LOAD VCO_SEL M0 M1 M2 M3 M4 M5 NA0 NA1 NA2 NB0 NB1 NB2 OE_REF , nP_LOAD M5:M0 NA2:NA0 NB2:NB0 CONFIGURATION INTERFACE LOGIC TEST 84334AY www.icst.com/products , Output of M divider CMOS Fout A0 SERIAL LOADING S_CLOCK S_DATA t T1 S T0 NB2 NB1 NB0 , PARALLEL LOADING M0:M5, NA0:NA2, NB0:NB2 nP_LOAD t S M, N t H Time FIGURE 1. PARALLEL & , , 19 20 21 22 Name NA2 NB0, NB1 NB2 OE_REF OE_A OE_B VCC nc VEE TEST FOUTA0, nFOUTA0 VCCOA FOUTB0 Integrated Circuit Systems
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RU1 6D diode

Abstract: ICS8430002 NB0 NB1 NB2 OE_REF OEA OEB 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 ICS8430002 33 48 , :NA0 NB2:NB0 Configuration Interface Logic TEST 3 3 ICS8430002AY REVISION C NOVEMBER 12 , T0 MFRAC11 NB2 MFRAC10 MINT5 NB1 MFRAC9 MINT4 NB0 MFRAC8 MINT3 NA2 , 4 NB2 Input Pulldown 5 OE_REF Input Pulldown 6 OEA Input Pullup , data present at NA2:NA0 and NB2:NB0 is loaded into the N output divider value. LVCMOS/LVTTL interface
Integrated Device Technology
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RU1 6D diode T3D 46 diode ICS8430002AL 7495 function table T3D 43 diode T3D 77
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