NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: transistor Hysteresis circuit built in · Low operation voltage Ordering Information Type NO. Marking , LH Transmission delay time tPLH 2 RL=4.7 , CL=100 - 100 500 HL Transmission delay time tPHL 2 RL=4.7 , CL=100 - 10 20 Hysteresis Voltage Temperature ... | Original |
4 pages, |
S7733SF S7727SF S7729SF S7731SF S7723SF S7736SF S7739SF S7742SF S7745SF S7725SF CL100 transistor transistor cl100 datasheet abstract |
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| Abstract: transistor Hysteresis circuit built in · Low operation voltage Ordering Information Type NO. Marking , 2 RL=4.7 , CL=100 - 100 500 HL Transmission delay time tPHL 2 RL=4.7 , CL=100 - 10 20 Hysteresis Voltage Temperature Coefficient Of detecting voltage Test ... | Original |
4 pages, |
S7733M S7727M S7729M S7731M S7723M S7736M S7739M S7742M S7745M S7725M CL100 transistor transistor CL100 datasheet abstract |
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| Abstract: of output transistor (IOL=20mA Typ.) · Hysteresis circuit built in (VS=100mV Typ.) · It has on , LH Transmission delay time tPLH 2 RL=4.7 , CL=100 - 100 500 HL Transmission delay time tPHL 2 RL=4.7 , CL=100 - 10 20 Characteristic Temperature ... | Original |
7 pages, |
9046 S72N25 S72N27 S72N29 S72N31 S72N33 S72N36 S72N39 S72N42 S72N45 CL100 transistor transistor cl100 datasheet abstract |
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| Abstract: transistor · Hysteresis Voltage is Provided Applications · As Control Circuit of Battery-Backed Memory , mA LH Transmission delay time tPLH 2 RL =1.0 , CL=100 - 15 - HL Transmission delay time tPHL 2 RL =1.0 , CL=100 - 10 - Temperature Coefficient of ... | Original |
6 pages, |
CL100 transistor S7125SF S7127SF S7129SF S7131SF S7133SF S7136SF S7139SF S7142SF S7145SF transistor cl100 KSD 75 datasheet abstract |
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| Abstract: of output transistor (IOL=20mA Typ.) · Hysteresis circuit built in (VS=100mV Typ.) · It has on , , CL=100 - 100 500 HL Transmission delay time tPHL 2 RL=4.7 , CL=100 - 10 ... | Original |
7 pages, |
S72N45UF S72N25UF S72N27UF S72N29UF S72N31UF S72N33UF S72N36UF S72N39UF S72N42UF 2056 datasheet abstract |
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| Abstract: of output transistor (IOL=20mA Typ.) · Hysteresis circuit built in (VS=100mV Typ.) · It has on , , CL=100 - 100 500 HL Transmission delay time tPHL 2 RL=4.7 , CL=100 - 10 ... | Original |
7 pages, |
transistor cl100 S72N27SF S72N29SF S72N31SF S72N33SF S72N36SF S72N39SF S72N42SF S72N45SF S72N25SF datasheet abstract |
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| Abstract: transistor · Hysteresis Voltage is Provided Applications · As Control Circuit of Battery-Backed Memory , Transmission delay time tPLH 2 RL =1.0 , CL=100 - 15 - HL Transmission delay time tPHL 2 RL =1.0 , CL=100 - 10 - Temperature Coefficient of Detecting Voltage ... | Original |
6 pages, |
S7125N S7127N S7129N S7131N S7133N S7136N S7139N S7142N S7145N transistor cl100 datasheet abstract |
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| Abstract: transistor · Hysteresis Voltage is Provided Applications · As Control Circuit of Battery-Backed Memory , mA LH Transmission delay time tPLH 2 RL =1.0 , CL=100 - 15 - HL Transmission delay time tPHL 2 RL =1.0 , CL=100 - 10 - Temperature Coefficient of ... | Original |
6 pages, |
sot89 "voltage detecting" marking datasheet abstract |
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| Abstract: IOUT=30 mA, VIN=4.2 V Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=4.2 V , Hz, CL=100 uF IOUT=30 mA, VIN=5 V * ±0.35 48 mV/°C dB Definition of , Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=5.2 V * ±0.40 48 mV/°C , IOUT=30 mA, VIN=5.3 V Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=5.3 V * 4 , 15 V IOUT=30 mA, VIN=5.5 V Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=5.5 ... | Original |
32 pages, |
REGULATOR S 813 S81350HG S-81350HG REGULATORS S 812 S-81332HG S-81330HG S-813 TRANSISTOR S 812 REGULATOR S 812 TRANSISTOR S 813 transistor CL100 S-81332HG-KC S-812 S-812 abstract |
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| Abstract: f=100 Hz, CL=100 uF IOUT=30 mA, VIN=4.2 V * ±0.26 35 mV/°C dB , IOUT=30 mA, VIN=5 V Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=5 V * ±0.35 , 15 V IOUT=30 mA, VIN=5.2 V Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=5.2 , Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=5.3 V * 4 ±0.40 48 mV/°C , Ta=-30°C to 80°C f=100 Hz, CL=100 uF IOUT=30 mA, VIN=5.5 V * ±0.41 48 mV/°C ... | Original |
31 pages, |
S-81350HG S-81332HG S-81330HG S-813 transistor CL100 s-81350hg-kd-x S-812 S-812 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| 80 o (CL = 100 pF, RL = 100K W ) Offset + 3 + 10 mV OTA11 OTA11 OTA11 OTA11 MOS Unity gain - bandwidth 24 advantage of the bipolar structure: l very high speed NPN transistor : f T = 6 GHz l very high speed NPN transistor P input CMOS Op-Amp Lateral PNP Crystal oscillator Substrate PNP RC oscillator converter N-MOS transistor Voltage reference P-MOS transistor 8 bits, A/D and D/A converters NPN high libraries included in the design flow: macro models and transistor level models, footprint, GDS2 layout www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2629-v3.htm |
STMicroelectronics | 25/05/2000 | 18.7 Kb | HTM | 2629-v3.htm |
| operational current consumption 360 uA Amplifier Phase margin 80 o (CL = 100 pF, RL = 100K W ) Offset speed NPN transistor : f T = 6 GHz l very high speed vertical PNP : f T = 2.5 GHz This allows high /10 Figure 2: The STKM2000 STKM2000 STKM2000 STKM2000 Series, a complete system solution ANALOG LIBRARY NPN transistor P input CMOS Op comparator Analog multiplexer P input comparator Voltage to current converter N-MOS transistor Voltage reference P-MOS transistor 8 bits, A/D and D/A converters NPN high-speed amplifier 12 bits A/D and D www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2629.htm |
STMicroelectronics | 20/10/2000 | 19.6 Kb | HTM | 2629.htm |
| margin 80 o (CL = 100 pF, RL = 100K W ) Offset + 3 + 10 mV OTA11 OTA11 OTA11 OTA11 MOS Unity gain - bandwidth 24 MHz transistor : f T = 6 GHz l very high speed vertical PNP : f T = 2.5 GHz This allows high gain - bandwith solution ANALOG LIBRARY NPN transistor P input CMOS Op-Amp Lateral PNP Crystal oscillator Substrate PNP RC current converter N-MOS transistor Voltage reference P-MOS transistor 8 bits, A/D and D/A converters NPN models and transistor level models, footprint, GDS2 layout, LVS netlist. Figure 3: Analog Design System www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2629-v2.htm |
STMicroelectronics | 14/06/1999 | 16.78 Kb | HTM | 2629-v2.htm |
| margin 80 o (CL = 100 pF, RL = 100K W ) Offset + 3 + 10 mV OTA11 OTA11 OTA11 OTA11 MOS Unity gain - bandwidth 24 MHz transistor : f T = 6 GHz l very high speed vertical PNP : f T = 2.5 GHz This allows high gain - bandwith solution ANALOG LIBRARY NPN transistor P input CMOS Op-Amp Lateral PNP Crystal oscillator Substrate PNP RC current converter N-MOS transistor Voltage reference P-MOS transistor 8 bits, A/D and D/A converters NPN models and transistor level models, footprint, GDS2 layout, LVS netlist. Figure 3: Analog Design System www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2629-v1.htm |
STMicroelectronics | 02/04/1999 | 16.82 Kb | HTM | 2629-v1.htm |
| KM68FV1000 KM68FV1000 KM68FV1000 KM68FV1000 2 KM68FV1000L KM68FV1000L KM68FV1000L KM68FV1000L 2 KM681000CL-L KM681000CL-L KM681000CL-L KM681000CL-L KM681000CL 100 n/a 1000 1000 1000 5000 7.6 7.6 Samsung KM68FV1000 KM68FV1000 KM68FV1000 KM68FV1000 2 KM68FV1000L KM68FV1000L KM68FV1000L KM68FV1000L 2 KM681000CL-L KM681000CL-L KM681000CL-L KM681000CL-L KM681000CL 100 n based on a 6-transistor cell, or a 4-transistor cell, as indicated by the references to 6T and 4T, respectively. By way of illustration, a one-bit storage cell from a 4-transistor SRAM cell is shown in Figure Appendix A. Figure 2. Four-Transistor (4T) SRAM Cell Category Devices ZEROPOWER (6T cell) M48Z08 M48Z08 M48Z08 M48Z08, M www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6395-v3.htm |
STMicroelectronics | 28/06/2000 | 48.14 Kb | HTM | 6395-v3.htm |
| KM68FV1000L KM68FV1000L KM68FV1000L KM68FV1000L 2 KM681000CL-L KM681000CL-L KM681000CL-L KM681000CL-L KM681000CL 100 n/a 1000 1000 1000 5000 10 000 20 000 105 n 681000CL-L 681000CL-L 681000CL-L 681000CL-L KM681000CL 100 n/a 1000 1000 1000 5000 10 000 20 000 675 n/a 1575 1575 1800 categories, as shown in Table 1. The SRAM array is generally based on a 6-transistor cell, or a 4-transistor -bit storage cell from a 4-transistor SRAM cell is shown in Figure 2. Table 1. ZEROPOWER and TIMEKEEPER battery lifetimes that has been included, for reference, in Appendix A. Figure 2. Four-Transistor (4T www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6395.htm |
STMicroelectronics | 20/10/2000 | 49.64 Kb | HTM | 6395.htm |
| 681000CL-L 681000CL-L 681000CL-L 681000CL-L KM681000CL 100 n/a 1000 1000 1000 5000 10 000 20 000 105 n/a 1005 1005 1100 5100 10100 20100 -L KM681000CL 100 n/a 1000 1000 1000 5000 10 000 20 000 675 n/a 1575 1575 1800 5800 10800 20800 > 20 n generally based on a 6-transistor cell, or a 4-transistor cell, as indicated by the references to 6T and 4T, respectively. By way of illustration, a one-bit storage cell from a 4-transistor SRAM cell is shown in Figure 2 lifetimes that has been included, for reference, in Appendix A. Figure 2. Four-Transistor (4T) SRAM Cell The www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6395-v1.htm |
STMicroelectronics | 02/04/1999 | 45.5 Kb | HTM | 6395-v1.htm |
| 681000CL-L 681000CL-L 681000CL-L 681000CL-L KM681000CL 100 n/a 1000 1000 1000 5000 10 000 20 000 105 n/a 1005 1005 1100 5100 10100 20100 -L KM681000CL 100 n/a 1000 1000 1000 5000 10 000 20 000 675 n/a 1575 1575 1800 5800 10800 20800 > 20 n generally based on a 6-transistor cell, or a 4-transistor cell, as indicated by the references to 6T and 4T, respectively. By way of illustration, a one-bit storage cell from a 4-transistor SRAM cell is shown in Figure 2 lifetimes that has been included, for reference, in Appendix A. Figure 2. Four-Transistor (4T) SRAM Cell The www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6395-v2.htm |
STMicroelectronics | 14/06/1999 | 45.46 Kb | HTM | 6395-v2.htm |
| ST | 8-BIT MICROCONTROLLER (MCU) WITH ROM, EPROM, OTP AND ON SCREEN DISPLAY (OSD) FOR TV FREQUENCY AND VOLTAGE SYNTHESIS Datasheet 8-BIT MICROCONTROLLER (MCU) WITH ROM, EPROM, OTP AND ON SCREEN DISPLAY (OSD) FOR TV FREQUENCY AND VOLTAGE SYNTHESIS ST63126B1 ST63126B1 ST63126B1 ST63126B1 ST63126 ST63126 ST63126 ST63126 ST63140B1 ST63140B1 ST63140B1 ST63140B1 ST63140 ST63140 ST63140 ST63140 ST63142B1 ST63142B1 ST63142B1 ST63142B1 ST63146 ST63146 ST63146 ST63146 ST63156B1 ST63156B1 ST63156B1 ST63156B1 ST63156 ST63156 ST63156 ST63156 ST63E126D1 ST63E126D1 ST63E126D1 ST63E126D1 ST63E140D1 ST63E140D1 ST63E140D1 ST63E140D1 ST63E142D1 ST63E142D1 ST63E142D1 ST63E142D1 ST63E156D1 ST63E156D1 ST63E156D1 ST63E156D1 ST63T126B1 ST63T126B1 ST63T126B1 ST63T126B1 ST63T140B1 ST63T140B1 ST63T140B1 ST63T140B1 ST63T142B1 ST63T142B1 ST63T142B1 ST63T142B1 ST63T156B1 ST63T156B1 ST63T156B1 ST63T156B1 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2517-v3.htm |
STMicroelectronics | 25/05/2000 | 180.57 Kb | HTM | 2517-v3.htm |
| ST | 8-BIT MICROCONTROLLER (MCU) WITH ROM, EPROM, OTP AND ON SCREEN DISPLAY (OSD) FOR TV FREQUENCY AND VOLTAGE SYNTHESIS ST63126 ST63126 ST63126 ST63126 8-BIT MICROCONTROLLER (MCU) WITH ROM, EPROM, OTP AND ON SCREEN DISPLAY (OSD) FOR TV FREQUENCY AND VOLTAGE SYNTHESIS Document Number: 2517 Date Update: 10/11/95 Pages: 86 The document is available in the following formats: Portable Document Format and Raw Text Format ST63140 ST63140 ST63140 ST63140, ST63146 ST63146 ST63146 ST63146 ST63126 ST63126 ST63126 ST63126, ST6 www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2517.htm |
STMicroelectronics | 02/04/1999 | 178.32 Kb | HTM | 2517.htm |