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SRIO-E3-UT1 Lattice Semiconductor Corporation SITE LICENSE SRIO 2.1 ECP3 visit Digikey Buy
SRIO-E3-U1 Lattice Semiconductor Corporation IP CORE SRIO 2.1 ENDPOINT ECP3 visit Digikey Buy

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Part : FC-GPCS-RIO16-PF Supplier : PEPPERL+FUCHS Manufacturer : Allied Electronics & Automation Stock : - Best Price : $998.1400 Price Each : $998.1400
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Part : SRIO-E3-UT1 Supplier : Lattice Semiconductor Manufacturer : Symmetry Electronics Stock : - Best Price : $36,619.7188 Price Each : $36,619.7188
Part : SRIO-PM-U1 Supplier : Lattice Semiconductor Manufacturer : Symmetry Electronics Stock : - Best Price : $12,206.5703 Price Each : $12,206.5703
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srio Datasheet

Part Manufacturer Description PDF Type
SRIO-E3-U1 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE SRIO 2.1 ENDPOINT ECP3 Original
SRIO-E3-UT1 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE SRIO 2.1 ECP3 Original

srio

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: : www.IDT.com/go/SRIOGen2 DSP S-RIO 2 Military Open VPX System SOFTWARE AND HARDWARE ECOSYSTEM â , x4 S-RIO Backplane x4 S-RIO CPS-1616 RapidIO Switch x1 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x1 S-RIO x4 S-RIO x1 S-RIO FPGA S-RIO CPS-1616 RapidIO Switch DSP S-RIO 2 DSP S-RIO 2 DSP S-RIO 2 PowerPC S-RIO CPS-1848 RapidIO Switch FemtoClock® NG 156.25 MHz FemtoClock® NG 156.25 MHz S-RIO 24 x 4 Switch Card S-RIO Integrated Device Technology
Original
REVC0211
Abstract: S-RIO x4 S-RIO Discover what IDT know-how can do for you: www.IDT.com/go/SRIOGen2 DSP S-RIO 2 , PHY Processing x4 S-RIO Backplane x4 S-RIO CPS-1848 RapidIO Switch SOFTWARE AND HARDWARE , IBIS models x4 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x4 S-RIO x4 S-RIO DSP S-RIO 2 DSP S-RIO 2 x4 S-RIO FPGA S-RIO RapidIO Switch DSP S-RIO 2 PowerPC S-RIO S-RIO 24 x 4 Switch Card S-RIO Payload Card Imaging Application RapidIO Switch Integrated Device Technology
Original
REVE0211

CPS-1848

Abstract: CPS 1848 Switch x4 S-RIO x4 S-RIO Discover what IDT know-how can do for you: www.IDT.com/go/SRIOGen2 , / CBSAI FPGA or ASIC OFDMA PHY Processing x4 S-RIO Backplane x4 S-RIO CPS-1848 RapidIO , ·HSPICE and IBIS models x4 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x4 S-RIO x4 S-RIO DSP S-RIO 2 DSP S-RIO 2 x4 S-RIO FPGA S-RIO RapidIO Switch DSP S-RIO 2 PowerPC S-RIO S-RIO 24 x 4 Switch Card S-RIO Payload Card Imaging Application
Integrated Device Technology
Original
REVC0910 CPS 1848 srio 4x4 calculator LTE ANTENNA GUIDE 1848 radar distance

CPS-1848

Abstract: CPS-1616 Discover what IDT know-how can do for you: www.IDT.com/go/SRIOGen2 DSP S-RIO 2 Military Open VPX , Antenna Interface CPRI / CBSAI FPGA or ASIC OFDMA PHY Processing x4 S-RIO Backplane x4 S-RIO CPS-1616 RapidIO Switch x1 S-RIO FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x1 S-RIO x4 S-RIO x1 S-RIO FPGA S-RIO CPS-1616 RapidIO Switch DSP S-RIO 2 DSP S-RIO 2 DSP S-RIO 2 PowerPC S-RIO CPS-1848 RapidIO Switch FemtoClock® NG 156.25 MHz
Integrated Device Technology
Original
Application of dsp in military sonar CPS1616 REVB0610
Abstract: errors x86 Processor + PCIe2 to S-RIO2 Bridge S-RIO CPU x4 PCIe PCIe Switch x4 P PCIe , /monitors Dedicated maintenance path for â'5th priorityâ' Error Management features exceeding S-RIO , S-RIO links, 1 with three 4x S-RIO links, AMC.0 and AMC.4 Specification (NO support on IPMC and JTAG) â'¢ 2 SFP+ Connectors: 1 ports with 1x S-RIO link, INF-8341 Specification â'¢ 1 QSFP Connectors: 1 port with 4x S-RIO link, SFF-8438i Specification â'¢ 2 InfiniBand/CX4 Connectors: 1 port Integrated Device Technology
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REVB0311

srio

Abstract: 80KSW0001 . Unicast: All other operations are performed as specified in sRIO. c. Maintenance packets: As specified in sRIO. The core of the Pre-Processing Switch are the Packet Processing Scenarios. The PPScs perform a , generation per sRIO packet Packet Trace ­ Each Port provides the ability to match the first 160 bits of , Scenarios (PPSc) u Interfaces - sRIO ­ 12 Serial RapidIO (sRIO) v 1.3 full duplex lanes ­ Lane Rates , software) ­ sRIO Multicast support (10 simultaneous masks) ­ Support for 4 sRIO priorities ­ Port
Integrated Device Technology
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80KSW0001 IDT70K2000 80KSW001
Abstract: to S-RIO2 CPS-1432 x86 CPU Tsi721 PCIe2 to S-RIO2 S-RIO Switch 18x1,18x2, 12x4 Rapid , Application x4 S-RIO Backplane p Antenna Interface CPRI/OBSAI x4 S-RIO Tsi721 PCIe2 to S-RIO2 x4 , Integrated DeviceTechnology Integrated DeviceTechnology Tsi721 PCIe2 to S-RIO2 Protocol , LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO FEATURES â'¢ x4 PCIe V2.1 to x4 S-RIO V2 , â'¢ Reach Support: 60 cm over 2 connectors â'¢ 100, 125, 156.25 MHz S-RIO and PCIe Endpoint Integrated Device Technology
Original
TSI721 REVD0711
Abstract: x4 S-RIO Discover what IDT know-how can do for you: www.IDT.com/go/SRIOGen2 DSP S-RIO 2 , ) Wireless Application Antenna Interface CPRI / CBSAI FPGA or ASIC OFDMA PHY Processing x4 S-RIO Backplane x4 S-RIO SOFTWARE AND HARDWARE ECOSYSTEM â'¢ Serial RapidIO Development Platform Gen2 , support â'¢ Power Calculator tool â'¢ HSPICE and IBIS models x4 S-RIO CPS-1432 RapidIO Switch FemtoClock® NG 156.25 MHz MAC Layer + Control Processor x4 S-RIO x4 S-RIO x4 S-RIO DSP Integrated Device Technology
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REVA0311

e500v2

Abstract: P2020 Mezzanine DDR II DDR SRIO/PCIe 4x SRIO/PCIe MUX LB DDR III Mini-USB SRIO 4x 4x SRIO SRIO I2C USB IPMB-L UART I2C Mezzanine DDR III Port 8:11 Port 17:20 4x eSDHC SRIO/PCIe Port 12:15 SRIO GigE Memory Card FPGA MSC8156 DDR DDR GigE GigE sRIO sRIO UART I2C Ethernet Port 4:7 MUX SRIO Switch SRIO Ethernet 1000 Base-X 4x SOCDIMM Flash Port 0 Port 1 P2020 GigE GigE PCIe/sRIO
Freescale Semiconductor
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P2020MSC8156RDFS e500v2 RGMII switch fpga rgmii MSC8156 datasheet p2020 processor registers DDR2-1600 P2020-MSC8156 DDR3-800

80KSW0004

Abstract: IDT80KSW0004 DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in , performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. If there is no match, the , . Features Interfaces - sRIO ­ 12 bidirectional serial RapidIO (sRIO) lanes v 1.3 ­ Port Speeds , Forward data flow ­ Device configurable through any of sRIO ports, I2C, or JTAG ­ Packet Trace/Mirror , configurable as line card, or backplane ports. It is an end-point free (switch) device in an sRIO network
Integrated Device Technology
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IDT80KSW0004 80KSW0004 CPS-12

backplane cps-16

Abstract: CPS-16 , processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in serial RapidIO , Interfaces - sRIO ­ 16 bidirectional serial RapidIO (sRIO) lanes v 1.3 ­ Port Speeds selectable: 3.125Gbps , Performance ­ 40 Gbps of peak switching bandwidth ­ Non-blocking data flow architecture within each sRIO , of sRIO ports, I2C, or JTAG ­ Packet Trace/Mirror/Filter. Per-port line rate copy or filter of all , ) device in an sRIO network. The CPS-16 receives packets from up to 16 ports. The CPS-16 offers full
Integrated Device Technology
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80KSW0002 backplane cps-16 LN12 CPRI CPS16

pcb thermal Design guide pcb trace

Abstract: pcb layout guide differential ohms stackup Serial Rapid I/O (SRIO) interface on the TMS320TCI6482 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previous approaches for , analog nature of SRIO, it is not possible to specify the interface in a traditional DSP digital , requirements laid out by the SRIO specification. Understanding the SRIO specification and producing a , , and expensive tools. For the TMS320TCI6482 SRIO interface, the approach is to reduce the
Texas Instruments
Original
pcb thermal Design guide pcb trace pcb layout guide differential ohms stackup RG142 RG178 RG316 TMS320TCI100

80KSW0003

Abstract: 324-ball , processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in serial RapidIO , : All other operations are performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. , optional broadcast) from any of its 8 input ports to any of its 8 output ports. Interfaces - sRIO ­ 8 bidirectional serial RapidIO (sRIO) lanes v 1.3 ­ Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps ­ , Gbps of peak switching bandwidth ­ Non-blocking data flow architecture within each sRIO priority ­
Integrated Device Technology
Original
80KSW0003 324-ball

IDT80KSW0004

Abstract: 80KSW0004 DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in , operations are performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. If there is , . Features Interfaces - sRIO ­ 12 bidirectional serial RapidIO (sRIO) lanes v 1.3 ­ Port Speeds , architecture within each sRIO priority ­ Very low latency for all packet length and load condition ­ Internal , Device configurable through any of sRIO ports, I2C, or JTAG ­ Packet Trace: Each port provides the
Integrated Device Technology
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PCIE SWITCH IDT

80HFC1000

Abstract: tdm RECEIVER any other sRIO-based devices. It may also be used in serial RapidIO backplane switching. The CPS , specified in sRIO. c. Maintenance packets: As specified in sRIO. 2) Enhanced Functions Enhanced features , 60 Gbps of peak switching bandwidth Non-blocking data flow architecture within each sRIO priority , any of sRIO ports, I2C, or JTAG ­ Packet Trace/Mirror/Filter. Per-port line rate copy or filter of , 16 input ports to any of its 16 output ports. 2 Features Interfaces - sRIO 24 bidirectional
Integrated Device Technology
Original
80KSW0006 80HFC1000 tdm RECEIVER CPS-6Q 80HFC1001 CPS-10Q

MSC8144EPB

Abstract: VOCODERS voip serial RapidIO interface or Ethernet. sRIO MSC8144E sRIO MSC8144E TDM 1xsRIO 4x/1x sRIO ETH ETH ETH I 2C UTOPIA 4x/1x sRIO PCI MSC8144E TDM ETH ETH I 2C UTOPIA PCI DDR sRIO TDM ETH PCI DDR I2C UTOPIA DDR 1xsRIO DDR SDRAM ETH sRIO DDR SDRAM MSC8144E sRIO MSC8144E TDM 1000Base-T ETH ETH ETH I 2C PCI DDR DDR SDRAM sRIO UTOPIA TDM ETH ETH I 2C UTOPIA PCI TDM
Freescale Semiconductor
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MSC8144EPB VOCODERS voip MPC8347E MSC8144 SC140 SC1400

8-port GbE PHY

Abstract: 80KSW0003 , processors, FPGAs, other switches, or any other sRIO-based devices. It may also be used in serial RapidIO , performed as specified in sRIO. c. Maintenance packets: As specified by sRIO. serial RapidIO ports. The , optional broadcast) from any of its 8 input ports to any of its 8 output ports. Interfaces - sRIO ­ 8 bidirectional serial RapidIO (sRIO) lanes v 1.3 ­ Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps ­ , Gbps of peak switching bandwidth ­ Non-blocking data flow architecture within each sRIO priority ­
Integrated Device Technology
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8-port GbE PHY

pcb thermal Design guide pcb trace

Abstract: RG316 Disabled. Loss-of-signal detection not used in SRIO. 13:12 ALIGN 01 Comma Alignment. SRIO uses , instructions for the Serial RapidIO® (SRIO) interface on the TMS320TCI6486/TMS320C6472 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite , digital bus design. Due to this analog nature of the SRIO, it is not possible to specify the interface in , in terms of the raw physical requirements laid out by the SRIO specification. Understanding the SRIO
Texas Instruments
Original
SPRU811 stackup TMS320TCI6486 RAPIDIO TMS320C6472/TMS320TCI6486
Abstract: LP-HCSL1 PCIe G1/G2, SGMII, sRIO 1x / 2x SATA / SATA3G Input Qty Input Type Output Qty , /G2/G3, 1.25 / 2.5 / 3.125 / 5 / 10; 1.5 / 3â' SGMII 1x/2.5x, sRIO 1x/1.25x/2x SATA/SATA3G , DIF HCSL 5 - 166 PCIe G1/G2/G3, sRIO 1x/2x SATA/SATA3G 2.5 / 5/8; 1.5 / 3â' 1 DIF/ 1 , , sRIO 1x/1.25x/2x SATA/SATA3G, XAUI, XAUI 10G 1.25 / 2.5 / 3.125 / 5 / 8 / 10; 1.5 / 3.0 (SATA) 1x 25 REF / 1x 50 REF LVCMOS / LVTTL * PCIe G1/G2, SGMII 1x / 2.5x, sRIO 1x / 1.25x / 2x Integrated Device Technology
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REVA0112

CPS-10Q

Abstract: SRIO40 for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. It , for broadcast. b. Unicast: All other operations are performed as specified in sRIO. c. Maintenance packets: As specified in sRIO. 2) Enhanced Functions Enhanced features are provided for support of , output ports. 2 Features Interfaces - sRIO 40 bidirectional serial RapidIO (sRIO) lanes v 1.3 , Performance 100 Gbps of peak switching bandwidth Non-blocking data flow architecture within each sRIO
Integrated Device Technology
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80KSW0005 SRIO40 CPS10Q
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