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BQ24026DRCR Texas Instruments bqTINY-II Dual Input USB/AC Adpater 1-Cell Li-Ion Charger w/Timer Enable & Temp Sense, No Taper 10-VSON -40 to 85 visit Texas Instruments Buy
CD4026BPWR Texas Instruments CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Display Enable 16-TSSOP -55 to 125 visit Texas Instruments Buy
BQ24026DRCRG4 Texas Instruments 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10, 3 X 3 MM, GREEN, PLASTIC, SON-10 visit Texas Instruments
CD4026BPWRE4 Texas Instruments 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 5-BIT UP DISPLAY DRIVER COUNTER, PDSO16, GREEN, PLASTIC, TSSOP-16 visit Texas Instruments
CD4026BE Texas Instruments CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Display Enable 16-PDIP -55 to 125 visit Texas Instruments Buy
CD4026BPWRG4 Texas Instruments CMOS Decade Counter/Divider with Decoded 7-Segment Display Outputs and Display Enable 16-TSSOP -55 to 125 visit Texas Instruments

scl 4026 ae pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

SM5308

Abstract: scl 4026 ae pin diagram Diagram I 2C Controller 10µF REF1 REF2 VDD REF3 SDA VCC1 SCL OUT1 VSS , I I I I I I I I REF1 1 28 REF2 VDD 2 27 REF3 SDA 3 26 VCC1 SCL 4 25 , °C Package: 28-pin HSOP 1.3TYP 18.6 ± 0.3 ORDERING INFORMATION Device Package SM5308AS 0.8 5.15 0.10 0.35 ± 0.05 0.12 M 0 to 10 ° 0.1 ± 0.05 I PINOUT 28-pin HSOP SEIKO NPC CORPORATION -1 SM5308AS BLOCK DIAGRAM VDD VSS ISET ADS REF1 SDA Vref
Nippon Precision Circuits
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SM5308 scl 4026 ae pin diagram diagram ic 4026 CD 1691 CB 8D-13 NC0418BE

SM5308

Abstract: similar ic BA 3812 BLOCK DIAGRAM VDD VSS ISET ADS REF1 SDA Vref Current Source I 2C Control SCL , mode (up to 400kbit/s) Operating ambient temperature range: 0 to 70°C Package: 28-pin VSOP (Top view) REF1 1 28 REF2 VDD REF3 SDA VCC1 SCL OUT1 VSS NC TEST , 9.8 ± 0.2 ORDERING INFORMATION SM5308AV 28-pin VSOP 0.10 ± 0.05 Package 1.15 ± 0.1 , SM5308AV PIN DESCRIPTION Number Name I/O*1 A/D*2 1 REF1 O A Internal reference
Nippon Precision Circuits
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similar ic BA 3812 pin diagram for IC cd 1619 cr BA 4213 tic 246 bd IC BA 3812 NC0510AE
Abstract: 9.9 ± 0.3 FEATURES 28-pin HSOP SEIKO NPC CORPORATION â'"1 SM5308AS BLOCK DIAGRAM VDD VSS ISET ADS REF1 SDA Vref Current Source I 2C Control SCL REF3 , SDA 3 26 VCC1 SCL 4 25 OUT1 VSS 5 24 NC TEST 6 23 GND1 ADS 7 22 VCC2 IN1 , temperature range: 0 to 70°C Package: 28-pin HSOP 1.3TYP 18.6 ± 0.3 ORDERING INFORMATION Device , PIN DESCRIPTION Number Name I/O*1 A/D*2 1 REF1 O A Internal reference voltage -
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Abstract: transfer rate: Fast mode (up to 400kbit/s) Operating ambient temperature range: 0 to 70°C Package: 28-pin VSOP (Top view) REF1 1 28 REF2 VDD REF3 SDA VCC1 SCL OUT1 VSS NC , 0.675TYP 9.8 ± 0.2 ORDERING INFORMATION SM5308AV 28-pin VSOP 0.10 ± 0.05 Package 1.15 , â'"1 SM5308AV BLOCK DIAGRAM VDD VSS ISET ADS REF1 SDA Vref Current Source I 2C Control SCL REF3 Bypass 0dB/6dB IN1 Clamp/Bias/Direct 5th order LPF (Standard -
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CY-320

Abstract: CY8C29X SCL P3[0], M, I2C1 SDA Pin Name P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Description Analog , Modes Ë EEPROM Emulation in Flash Programmable Pin Configurations Ë 25 mA Sink, 10 mA Drive on All GPIO , 128K Trace Memory I System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog , Block Diagram .1 Contents , .11 20-Pin Part Pinout .11 28-Pin Part Pinout
Cypress Semiconductor
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CY-320 CY8C29X CY8C28x52 56-pin 7x7 QFN cy8c28000 cy8c27x4 CY8C28243 CY8C28403 CY8C28413 CY8C28433 CY8C28445 CY8C28452

cy8c28000-24pvxi

Abstract: 56-pin 7x7 QFN ] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] I2C1 SDA, M, P3[0] Pin No. Active high external reset with , ] I2C1 SCL, M, P1[6] M, P5[0] M, P5[2] 8 9 10 11 12 13 14 15 16 17 Pin Name 48 47 , SDA, M, P1[5] NC M, P1[3] SCLK, I2C0 SCL, XTALIn, M, P1[1] Vss P3[5] 19 CY8C28000 56-Pin , Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 PSoC CORE System Bus Global Digital , ANALOG SYSTEM Analog Block Array Digital Block Array Programmable Pin Configurations 25 mA
Cypress Semiconductor
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cy8c28000-24pvxi graphical LCD PSoc BA RW QFN 64 8x8 footprint CY8C28513 CY8C28533 CY8C28545 CY8C28623 CY8C28643 CY8C28645

QFN-48 footprint

Abstract: cy8c28000-24pvxi ] I2C1 SCL, M, P1[6] I2C1 SDA, M, P3[0] Pin No. Active high external reset with internal pull , SCL, M, P1[6] M, P5[0] M, P5[2] 8 9 10 11 12 13 14 15 16 17 Pin Name 48 47 46 , SDA, M, P1[5] NC M, P1[3] SCLK, I2C0 SCL, XTALIn, M, P1[1] Vss P3[5] 19 CY8C28000 56-Pin , Memory System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 PSoC CORE System Bus , Pin Configurations 25 mA Sink, 10 mA Drive on All GPIO Cypress Semiconductor Corporation
Cypress Semiconductor
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QFN-48 footprint CY8C28452-24PVXI ACC02 85Y12 CY8C28xxx digi-key
Abstract: global buses that can route any signal to any pin. Figure 1. Digital System Block Diagram[1] Port 5 Port , Pin Configurations 25 mA Sink, 10 mA Drive on All GPIO Pull Up, Pull Down, High Z, Strong, or Open , Breakpoint Structure 128K Trace Memory System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port , the System Block Diagram on page 1, consists of four main areas: PSoC Core, Digital System, Analog , digital and analog resources. Each pin's drive mode may be selected from 8 options, which allows great Cypress Semiconductor
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NXP Semiconductor - MCU

Abstract: input, I2C SCL, ISSP SCL Ground Pin GPIO, Xtal output, I2C SDA, ISSP SDA GPIO GPIO, External clock IP , Programmable pin configurations 25 mA Sink, 10 mA source on all GPIO Pull-up, pull-down, high Z, strong, or , Block Diagram Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital , . 9 32-Pin Part Pinout . 9 28-Pin Part Pinout , range of convenient pinouts and packages. The PSoC architecture, as shown in the Logic Block Diagram on
Cypress Semiconductor
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NXP Semiconductor - MCU CY8C23433 CY8C23533

4026 manual digital counter circuit with reset

Abstract: capacitive touch key sensor cypress MCU SCL Ground Pin [6] GPIO, Xtal Output, I2C SDA, ISSP SDA GPIO 17 I/O P1[4] GPIO , Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Logic Block Diagram Port 3 Port 2 , 4 Blocks Programmable Pin Configurations 25 mA Sink, 10 mA Source on all GPIO Pull up, Pull , . 9 32-Pin Part Pinout . 9 28-Pin Part , . Digital System Block Diagram Port 3 Port 2 To System Bus Digital Clocks FromCore The PSoC
Cypress Semiconductor
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4026 manual digital counter circuit with reset capacitive touch key sensor cypress MCU CPU 414-3 Processor Module
Abstract: input, I2C SCL, ISSP SCL Ground Pin GPIO, Xtal output, I2C SDA, ISSP SDA GPIO GPIO, External clock IP , Programmable pin configurations 25 mA Sink, 10 mA source on all GPIO Pull-up, pull-down, high Z, strong, or , Block Diagram Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital , . 9 32-Pin Part Pinout . 9 28-Pin Part Pinout , range of convenient pinouts and packages. The PSoC architecture, as shown in the Logic Block Diagram on Cypress Semiconductor
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2650 cpu

Abstract: 4026 manual digital counter circuit with reset /O 28 Power GPIO [6] GPIO, Xtal input, I2C SCL, ISSP SCL Ground Pin [6] GPIO , programmer Full speed emulation Complex breakpoint structure 128 KB trace memory Logic Block Diagram , Columns 4 Blocks 1 Row 4 Blocks Programmable pin configurations 25 mA Sink, 10 mA source on all , . 9 32-Pin Part Pinout . 9 28-Pin Part , . Figure 1. Digital System Block Diagram Port 3 Port 2 Port 0 To System Bus Digital Clocks
Cypress Semiconductor
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2650 cpu
Abstract: , Xtal input, I2C SCL, ISSP SCL Ground Pin [6] GPIO, Xtal output, I2C SDA, ISSP SDA GPIO P2[2 , ' Full speed emulation Ã' Complex breakpoint structure Ã' 128 KB trace memory Logic Block Diagram , pin configurations Ã' 25 mA Sink, 10 mA source on all GPIO Ã' Pull-up, pull-down, high Z, strong, or , . 9 32-Pin Part Pinout . 9 28-Pin Part , . Figure 1. Digital System Block Diagram Port 3 Port 2 To System Bus Digital Clocks FromCore Cypress Semiconductor
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Abstract: SCL, ISSP SCL Vss Ground pin P1[0][4] GPIO, Xtal output, I2C SDA, ISSP SDA P1[2] P1[4] P1[6] XRES P2[0 , pin configurations 25 mA sink on all GPIO Pull-up, pull-down, high Z, strong, or open drain drive , 95134-1709 · 408-943-2600 Revised November 19, 2012 CY8C24633 Block Diagram Port 3 Port 2 Port 1 Port , Features . 1 Block Diagram , . 10 28-Pin Part Pinout . 10 56-Pin Part Cypress Semiconductor
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Abstract: 13 I/O 14 P1[1][4] GPIO, Xtal input, I2C SCL, ISSP SCL Power Vss Ground pin P1[0 , ' Partial flash updates Ã' Flexible protection modes Ã' EEPROM emulation in flash I Programmable pin , , 2012 CY8C24633 Block Diagram Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE , Diagram . 2 Contents , . 10 28-Pin Part Pinout . 10 Document Number Cypress Semiconductor
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Abstract: SCL, ISSP SCL Vss Ground pin P1[0][4] GPIO, Xtal output, I2C SDA, ISSP SDA P1[2] P1[4] P1[6] XRES P2[0 , pin configurations 25 mA sink on all GPIO Pull-up, pull-down, high Z, strong, or open drain drive , 95134-1709 · 408-943-2600 Revised April 24, 2012 CY8C24633 Block Diagram Port 3 Port 2 Port 1 Port , Features . 1 Block Diagram , . 10 28-Pin Part Pinout . 10 56-Pin Part Cypress Semiconductor
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band pass

Abstract: 27p06 13 I/O P1[1][4] GPIO, Xtal input, I2C SCL, ISSP SCL Power 14 Vss Ground pin P1[0 , updates Flexible protection modes EEPROM emulation in flash Programmable pin configurations , Diagram Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital , . 1 Block Diagram . 2 Contents , . 10 28-Pin Part Pinout . 10 Document Number
Cypress Semiconductor
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band pass 27p06 pin configuration of CD 4026

cy8c24633

Abstract: CY8C24x33 ] GPIO, Xtal input, I2C SCL, ISSP SCL Power 14 Vss Ground pin P1[0][4] GPIO, Xtal output , Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin , ] Feedback CY8C24633 Block Diagram Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE , . 9 28-Pin Part Pinout . 9 56-Pin Part , System Block Diagram Port 3 PSoC GPIOs provide connection to the CPU, digital and analog resources
Cypress Semiconductor
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CY8C24x33

diode F4 9a

Abstract: applications touch switch cd 4011 pin configurations 25 mA sink, 10 mA source on all GPIOs Pull-up, pull-down, high Z, strong, or open , Diagram Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM , . 8 20-Pin Part Pinout . 8 28-Pin Part Pinout , of convenient pinouts and packages. The PSoC architecture, as shown in the Logic Block Diagram on , , which are called user modules. Figure 1. Digital System Block Diagram Port 1 Port 2 Port 0 Digital
Cypress Semiconductor
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diode F4 9a applications touch switch cd 4011 CY8C24223A CY8C24423A 48-MH

diode F4 9a

Abstract: 4026 manual digital counter circuit with reset pin configurations 25 mA sink, 10 mA source on all GPIOs Pull-up, pull-down, high Z, strong, or open , Diagram Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM , . 8 20-Pin Part Pinout . 8 28-Pin Part Pinout , Logic Block Diagram on page 1, is comprised of four main areas: PSoC core, digital system, analog system , Diagram Port 1 Port 2 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL
Cypress Semiconductor
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4026 block diagram for digital clock CY8C24423A-24PVXA
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