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Part Manufacturer Description Datasheet BUY
7704201FA Texas Instruments 4-By-4 Register Files With 3-State Outputs 16-CFP -55 to 125 visit Texas Instruments
SN74LS670NSR Texas Instruments 4-by-4 register files with 3-state outputs 16-SO 0 to 70 visit Texas Instruments
SNJ54LS670W Texas Instruments 4-By-4 Register Files With 3-State Outputs 16-CFP -55 to 125 visit Texas Instruments
CD74HC670E Texas Instruments High Speed CMOS Logic 4-by-4 Register File 16-PDIP -55 to 125 visit Texas Instruments
CD74HCT670EE4 Texas Instruments High Speed CMOS Logic 4-by-4 Register File 16-PDIP -55 to 125 visit Texas Instruments
CD74HC670EE4 Texas Instruments High Speed CMOS Logic 4-by-4 Register File 16-PDIP -55 to 125 visit Texas Instruments

register file

Catalog Datasheet MFG & Type PDF Document Tags

8 BIT ALU

Abstract: register file next cycle. The computation units input data from and output data to a 10-port register file that consists of sixteen primary registers and sixteen alternate registers. The register file is accessible to , and external memory or other parts of the processor. The individual registers of the register file , REGISTER FILE MULTIPLIER SHIFTER ALU 16 x 40-bit MR2 MR1 MR0 Figure 2.1 Computation , Multifunction Computations Register File and Data Transfers 2.2 IEEE FLOATING-POINT OPERATIONS The
Analog Devices
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2901s

Abstract: 4 bit ALU USING VLSI counter-type operations where constants may be in the register file in order CORDIC-type algorithms. Put , high-speed, fully cascadable 16-bit CMOS ALU slice with 64-by-16-bit register file. It combines the , from the D inputs into the register file and Q register. Normally, the loading of the register file , direct data input path through the ALU and then store the results in the register file or Q register. With the new data path, the data can be put directly into the register file in parallel with other
Integrated Device Technology
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weitek 1066

Abstract: WEITEK WTL 1066 32 x 32 SIX PORT REGISTER FILE Features HIGH SPEED 32-BIT x 32-WORD REGISTER FILE , SUBSYSTEMS Description The WTL 1066 register file directly supports the WTL 1232/1233, WTL 2264/2265 and WTL 1264/1265 floating point subsystems. The register file has 32 words, each 32-bits wide, which are , major cycle. The WTL 1066 register file provides the necessary data bandwidth to fully utilize WEITEK , ported register file makes it possible to achieve high pipeline utilization in a wide variety of
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weitek 1066 WEITEK register file Weitek 1233 WTL1232 wtl 1232 CH-1227

register file

Abstract: ADSP-2100 -bit data values. The register file source or destination of such an access is two adjacent data registers , significant 8 bits forced to zero on stores and truncated on loads. The register file source or destination , -bit accesses. The register file source or destination of such an access is a single 40-bit data register with , -bit width accesses occur as the result of an access to short word address space. The register file source , DATA BUS MUX 64 HOST PORT MULT DATA REGISTER FILE (PEx) 16 x 40-BIT BARREL SHIFTER
Analog Devices
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ADSP-21160 ADSP-2100 ADSP-21000 RND32

register file

Abstract: INTEL DX2 & Register file 3. Addressing Modes 4. Interrupt Controller 5. DMA Description 6. RCCU 7 , STACK POINTER FILE MICRO REGISTER SEQUENCER MMU Memory Management Unit FILE , FOR MEMORY (16 bits) AND REGISTER FILE (8 bits) - 6-bit BUS FOR INTERRUPT AND DMA (output on emulator , Processing Unit with a 8/16 bit Arithmetic Unit The Register File consisting of 256 Registers (directly , , byte, word data 14 addressing modes ® ST9+ TRAINING / CORE / 6 2. REGISTER FILE ST9
STMicroelectronics
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INTEL DX2 R223 R240 R244 R245 R255

register file

Abstract: 3 bit magnitude comparator -bit register file â'¢ Bit, byte, 16-bit and 32-bit operations â'¢ Configurable as quad 8-bit or dual 16 , 64-word register file is 36 bits wide to permit storage of the parity bits. Master/slave comparator , -word by 36-bit register file. Data and parity from the register file can be output on the DA and DB ports , an input mode to furnish external data to the register file or during master/slave operation as an , operand write to be performed at the register file simultaneously. An MQ shifter and MQ register can also
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AS888 3 bit magnitude comparator AS8832 sn74as8832 SN74AS8832 74AS8832 SIM74AS8832 DA/B31-DA/BO Y31-Y0

register file

Abstract: sm8521 cpu Addressing Mode Summary NAME implied Register Register pair Register file r rr R r = R0-R7 r = RRO, RR2, . . , [byte] General register [word] Register file (00 û 0 h-007F h) and (OOSOH-OOFFh) [byte] Register file , (OOOOh-FFFF h) [word/byte] : Memory (OOOOh-FFFF h) [word/byte] Register file pair Register indirect , code [word] Register file (0000 h-007F h) and memory (0080 h-00FF h, FFOOh-FFFFh) [bit] (1 bit of 1 , DAs DAp @DA Register file (0010 h-0017 h) [byte] PC - 128 to PC + 127 DA = OOOOh-FFFF h DAs =
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SM85CPU sm8521 cpu SM8521

register file

Abstract: B20B PRODUCT PREVIEW SNS4AS8834, SN74AS8834 40 BIT REGISTER FILE D 2936, N O V EM B ER I9 8 5 - R E , -Bit Register File Supports 'A S 8 8 8 and 'A S8 8 3 2 Register File Expansion logic sym b ol t 109-001 , . SN54AS8834, SN74AS8834 40-BIT REGISTER FILE SN 54A S8834. SN 74A S8834 G B PIN -G R ID -A R R A Y P A C K , , T E X A S 75265 SN54AS8834, SN74AS8834 40 BIT REGISTER FILE PIN N AM E NO. I/O D ESC R IP , ; low selects D A 20-D A 39. Clocks data into register file on rising edge. C LK DO D1 D2 D3 D4 D5 D6
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B20B Parity Checkers d2936 IO29D20 156-P IDA39-OA20 IDB190B0I IOA19-DAO ID839DB20

register file

Abstract: st9 technical manual limited. On ST9 devices, the system stack may be located in the Register File or in data memory space , . Figure 1. Example of Stack overflow detection in Register File Register File system registers System , initializes the system stack in groups D and C of the Register File. In the stack management of the ST9, the , the Register File, while the instruction: ld SSPLR,#SSTACK + 1 initializes the system stack pointer , Declaration and end of stack initialisation ; in RAM space or Register File
STMicroelectronics
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st9 technical manual st9 technical AN421 r235

MCS-96 architecture overview

Abstract: MCS-96 Register File; evenly divisible by four * LONG-INTEGER * 32 Yes -2,147,483,648 through +2,147,483,647 Even byte address in on-chip Register File; evenly divisible by four * * The 32-bit operands are , Register File. The MCS-96 architecture requires that bits be addressed as components of BYTEs or WORDs. It , on-chip Register File and must be aligned at an address that is evenly divisible by four. The address of a , -by-16 multiply operations. For these operations, a LONG-INTEGER variable must reside in the on-chip Register File
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PLM-96 MCS-96 architecture overview mcs 96 programming 80C196KC instruction set mcs-96 instruction set 80C196KC 8XC196KC/KD 8096BH

weitek 3332-100

Abstract: weitek 3132 /ACCUM ULA TORS W ITH FOUR PORT 32 x 32-BIT REGISTER FILE AND DIVIDE LOGIC UNIT FULL FUNCTION A dd , the WTL 3132, a four-port 32 x 32-bit register file and three temporary registers (where operands and , , CWEN Aadd - Dadd 32 x 32 REGISTER FILE R O VFLUN FL ZERO COND i A MUX A BUS 32 Bi MUX , . Neutralize (NEUT-) W hen Neutralize is asserted, the register file or tempo rary register Write, specified by , absence of code. Abort (ABORT-) W hen ABORT- is asserted, the register file or tempo rary registers WRITE
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weitek 3332-100 weitek 3132 3332 weitek 3332-G wtl3132 weitek 3332 3132/WTL

mcs-96 instruction set

Abstract: MCS-96 architecture overview Register File (Notel ) RALU Microcode Engine Watch Dog Timer Pulse Width Mod Clock Gen Interrupt , Register/Arithmetic Logic Unit (RALU) and a Register File. A0079-00 Figure 2-2. Block Diagram of the , words from either the 256-byte lower Register File or through a window that directly accesses the upper Register File. CPU instructions move from the four-byte queue in the memory controller into the RALU , that cause desired functions to occur. 2.2.2. Register File The Register File is divided into an
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8XC196KC 8XC196KC Users manual 8XC196KD users manual 8XC196KC instruction set mcs96 instruction set 8XC196KC instructions mcs 96 instructions 8XC196KD

0000H-FFFFH

Abstract: CKC Digital Timer Register Lineup Address Space ROM Area Register File Area RAM Area Data Format Bus Timing SYSTEM , register [byte] Register pair rr r = RR0, RR2, . , RR14 Register file R R = 0 to 255 (R0-R15) General register [word] Register file (0000H-007FH) and (0080H-00FFH) R = 0, 2, . 254 [byte] Register file (0000H-007FH) and (0080H-00FFH) [byte] Memory (0000H-00FFH) [byte] Register file pair RR Register indirect @r (RR0, RR2, . , RR14) r = R0-R7 Register indirect
Sharp
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0010H-0017H 0000H-FFFFH QFP128-P-1420 CKC Digital Timer SGDA 4 digit 7 segment display 28 pin micro controler VA1106 32x160 FF00H-FFFFH 1000H-FFFFH 1000H-1FFFH LH1527

register file

Abstract: 00H-03H for the Z8® MCU: s s The Z8 Standard Register File contains addresses for peripheral, control, all general-purpose, and all I/O port registers. This is the default register file specification , data only, whether internal or external. The Z8 Expanded Register File (ERF) contains addresses , FILE The Z8 Standard Register File totals up to 256 consecutive bytes (Registers). The register file , (F0H-FFH). Table 2-1 shows the layout of the register file, including register names, locations, and
ZiLOG
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00H-03H UM97Z8X0104 04H-EFH

register file

Abstract: 00FF data register file and three computation units: an arithmetic/logic unit (ALU), a multiplier, and a , through a 10-port register file, consisting of sixteen primary registers and sixteen alternate registers. Two ports on the register file connect to the PM and DM data buses, allowing data transfer between , . For information on the data register names, see "Data Register File" on page 2-29 Figure 2-1 , the register file. Most ALU operations return one result; in add/subtract operations, the ALU
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00FF double through put multiply accumulate

register file

Abstract: 54SX-A double-word register file and two state machines. The register file can be clocked at either the PCI rate or , the data through the register file. One of the state machines runs at the PCI rate and the other runs at the back-end rate to load and unload the register file. The back-end state machine can be , transferred to and from the register file in either one or four, 32-bit wide word sub-bursts. Four-word , blocks shown in Figure 2 on page 3. These blocks are the register file, the PCI-loading state machine
Actel
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54SX-A bgn-tn A54SX A54SX72A A54SX16A A54SX16P A54SX32A

register file

Abstract: d2936 PRODUCT PREVIEW SN54AS8B34, SN74AS8834 40-BIT REGISTER FILE d2936, november 1985 , File â'¢ Supports 'AS888 and AS8832 Register File Expansion â'¢ Four 10-Bit Input Ports with , files in a 1 56-pin ceramic pin grid array. The register files are designed to support register file , «HB-BS WiL-üüi «SjltliU^ 40-BIT REGISTER FILE â  A SB 8 34 IO9-D0I 1019-0101 1O29-D201 (D39-D301 , Respective Manufacturer SN54AS8834, SN74AS8834 40-BIT REGISTER FILE sn54as8834. sn74as8834 gb
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IDA190A0I D20-D29 036 84, 036 85, 036 86 rondorex w21 TRANSISTOR Y1D SN74AS883 rab5 PS1J MSH 119 IDA39-DA20I 119-O IDB39 Y9-Y01 Y19-Y101

register file

Abstract: UM97Z8X0104 exception of immediate data and condition codes, all operands are expressed as register file, Program , source address specified corresponds to the actual register in the register file. Register File Program Memory 8-Bit Register File Address dst One Operand Instruction (Example) OpCode Operand Points to One Register in the Register File Figure 11-1. 8-Bit Register Addressing In 4 , Register Pointer to form the actual 8-bit address of the affected register. Register File RP
ZiLOG
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00H-FFH

trackball interface

Abstract: register file . The Z86LXX architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File , configurations: Program Memory, Register File, Expanded Register File, and External Memory. The register file is , rest are General Purpose registers. The Expanded Register File consists of two additional register , /Low-Voltage Microcontroller P00 P01 P02 P03 Pref1 P31 P32 P33 Register File 256 x 8-bit 4 , 1 P34 P35 P36 P37 Z8 Core Internal Data Bus 8 Port 1 Expanded Register File
ZiLOG
Original
Z86L88 Z86L81 Z86L86 Z86L87 Z86L89 Z86L73 trackball interface circuit diagram of 16 bit counter 32 bit microcontroller architecture Z86L88/81/86/87/89/73

register file

Abstract: 2019H External Memory + 4 1FFH OH 3FFH OH Register File * Always write Ports 3 and 4 as a single word , 200H-1FFDH 512-6189 400H-1 FFDH 1024-8189 Register File (includes SFRs) 0H-1FFH 0-511 0H-3FFH 0-1023 NOTES , Register File are always assigned to external memory or I/O (see Figure 4-1 or Table 4-1). The 8XC196KC/KD , Memory \ Lower Interrupt Vectors 1FFH 3FFH Register \ \ \ 2000H OH OH File A0090-D0 Figure , (see Appendix C, "8XC196KC/KD Registers"). 4-5 Intel. MEMORY PARTITIONS 4.4. REGISTER FILE The
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0A000H-0FFFFH 2019H memory interface 8255 8XC196KC chapter 4 memory partitions 0H17H 8XC196KC chapter 5 interrupts 8216 INTEL 6000H 0A000H 2080H 207FH A0024-B0 6000H-0FFFFH
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