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LT5400AHMS8E-3#PBF Linear Technology LT5400 - Quad Matched Resistor Network; Package: MSOP; Pins: 8; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LT5400BMPMS8E-7#PBF Linear Technology LT5400 - Quad Matched Resistor Network; Package: MSOP; Pins: 8; Temperature Range: -55°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LT5400BMPMS8E-3#TRPBF Linear Technology LT5400 - Quad Matched Resistor Network; Package: MSOP; Pins: 8; Temperature Range: -55°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LT5400ACMS8E-2#TRPBF Linear Technology LT5400 - Quad Matched Resistor Network; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LT5400AIMS8E-2#TRPBF Linear Technology LT5400 - Quad Matched Resistor Network; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LT5400BHMS8E-1#TRPBF Linear Technology LT5400 - Quad Matched Resistor Network; Package: MSOP; Pins: 8; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy

ras2 resistor

Catalog Datasheet MFG & Type PDF Document Tags

ms-6535

Abstract: 4116 lf 165 ns 410 ns 515 ns vbb 1 [ O 2 ( w 3 (' räs1» 4 i räs2* s ao 6 a2 7 (. al 'dd a 9 1 , 1: RAS1 and CAS1 apply. Pins 5 and 16 are No-Connects Module 2: RAS2 and CAS2 apply. Pins 4 and 17 , Series74TTL circuits including clocks: Row Address Strobes RAS1 and RAS2, and Column Address Strobes, CAS1 and , the same procedure is followed, however addresses are now strobed in using row-address-strobe 2
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OCR Scan

4164 64k dram

Abstract: S41128B connect. RAS2 (pin 4) selects the upper DRAM, and pin 4 on th e low er DRAM is a no connect. PIN NOMENCLATURE A 0 -A 7 CAS D Q RÄS1, RÄS2 Vd D V ss Address Inputs Column-Address Strobe Data In Data Out , low on the RAS2 input selects the upper DRAM. The T M S 41128B-15 features a RAS access time of 150 ns , , and during this period each of the 256 rows m ust be strobed w ith RAS1 and RAS2 in order to retain , row-address strobe (RAS1 or RAS2). Then the eight column-address bits are set up on pins AO through A7 and
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OCR Scan
S41128B 4164 64k dram tms4164 Z41H 072-BIT 16-PIN

tms41128

Abstract: TMS4164 ) selects the lower DRAM, and pin 3 on the upper DRAM is a no connect. RAS2 (pin 4) selects the upper DRAM , NOMENCLATURE A0-A7 Address Inputs CAS Column-Address Strobe D Data In Q Data Out RASI, RAS2 Row-Address , lower DRAM; a logic low on the RAS2 input selects the upper DRAM. The TMS41128B-15 features a RAS , RAS2 in order to retain data. CAS can remain high during the refresh sequence to conserve power. All , by the row-address strobe (RAS1 or RAS2). Then the eight column-address bits are set up on pins AO
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OCR Scan
tms41128 TMS41128B 1985-REVISED A11AAAAAA

TMS4116

Abstract: TMS4132 LATU R E A 0 -A 6 Ò ASI C AS2 0 Q Aa £ i RAS2 A d d re s s In pu ts w W rite Enable S-V p o w e i s u p , are compatible with Series 74 TTL circuits including clocks: Row Address Strobes, RAS1 and RAS2, and , followed, however addresses are now strobed in using row-address-strobe 2 (RAS2)and column address strobe 2 (CAS2). When RAS1 and CAS 1 are being used (i.e. Module 1 selected), RAS2 and CAS2 should be high (and , RAS2) and CAS1 (or CAS2). Each RAS is sim ilar to a chip enable in that it activates the sense
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OCR Scan
TMS4116 TMS4132 768-BIT 18-PIN 300-M 4132JD
Abstract: . RASO and RAS2 select the words in the first bank while RAS1 and RAS3 select the second-bank words, if the SIMM is so equipped. · Note that the ECC SIMMs do not need RAS2, RAS3, CAS2 or CAS3. This , A8 A9 RAS3 RAS2 - A8 A9 RAS3 RAS2 PQ26 PQ8 A8 A9 DQ17 DQ18 A8 A9 DQ17 DQ18 Vss V ss , SIMM family. Presence detect ouputs must be tied to V cc through a pullup resistor to generate a , a 2.6K f i resistor. Page 1360 -
OCR Scan

N2964BN

Abstract: 2964B PACKAGE/PIN DESIGNATIONS PIN NO. IDENTIFIER FUNCTION 1, 2, RAS2, RAS3 Row Address Strobe outputs (RÃ"S , input. During normal memory cycles, the selected RAS Decoder output, RAS0, RAS, RAS2 or RAS3, will go , of four banks of memory with RAS0, RAS, RAS2 or RAS3. PIN NO. 10 11, 14, 18, 21, 24, 28, 32 and , as an address input for 64K DRAMs. If A,5 is pulled up to +12V through a 1K resistor, the terminal , decoder outputs, RAS0, RAS-i, RAS2 and RAS3, go LOW in response to a LOW input at RASI. This action
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OCR Scan
2964B N2964BN WE772 N2964BI Dynamic Memory Refresh Controller 016-K 27-BIT

2964B

Abstract: N2964BI and 40 4 and 5 IDENTIFIER FUNCTION RAS2, RAS3 Row Address Strobe outputs (RAS,). Each RAS0, RASi , selected RAS Decoder output, RAS0, RAS, RAS2 or RAS3, will go active LOW in response to an active LOW , ) is decoded by the RAS Decoder to "RAS Select" one of four banks of memory with RAS0, RÃ"5i, RAS2 or , 1K resistor, the terminal count output TC will go LOW every 128 counts (for 16K DRAMs) instead of , one-of-four to four-of-four so that all four RAS decoder outputs, RAS0, RA§1, RAS2 and RAS3, go LOW in
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OCR Scan

transistor K52

Abstract: TM31 25 26 27 28 29 30 31 32 Pin name #CE5/#CE15 #CE6 #CE7/#RAS0/#CE13/#RAS2 #CE8/#RAS1 , #CE7/#RAS0/#CE13/#RAS2 E0C33A104 s PIN DESCRIPTION q Power Supply, Clock Pin name VDD x6 , 7 I E0C33A104 test pin (no pull-up resistor) Fix at high level in normal operation. [1]:100 [0]:101 [1]:97 [0]:98 I Built-in ARAM mode setting (no pull-up resistor) Set according to the ARAM mode to be used. 56 53 I E0C33A104 test pin (no pull-up resistor) Fix at high level in normal
Seiko Epson
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transistor K52 TM31 QFP15-128 73a174 2 pin crystal oscillator 20mhZ 4 bit by bit 4 multiplication IC PF883-03 E0C33000
Abstract: . Ground DQ0 - D Q 7 0 *.Data Input/Output RAS0, RAS2 . . . . Row Address Strobe GO, G 2 , 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Name VSS G2 RAS2 CAS4 CAS6 WË2 VCC NC NC DQ18 DQ19 VSS , resistor to V c c at *he ne*t higher level of assembly. PDs are buffered and gated to the edge connector by -
OCR Scan
MCM64400
Abstract: ) · · · · · · RA0 to RA9, CAS0 and CAS1, RAS0 to RAS2, LWE, UWE, OE, SSP2/1, RAPC, WAPC, H11T0, LDH , , SUA0 to SUA7, CS D0 to D7 IO0 to IO15 RA0 to RA9, RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE WOBBLE , . This pin must be tied to VSS. 83 VCNT I VCO control voltage VCO bias resistor connection , RAS0 O 195 RAS1 O 196 RAS2 O 197 LWE O DRAM lower write enable 198 , lines. RAS0, RAS1, RAS2 (output) Buffer DRAM RAS outputs. Normally, RAS0 is used. However, if two 16 SANYO Electric
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LC898093 3210-SQFP208
Abstract: , LDH, ATEST3, ATEST1, WDAT, NWDAT (8) . PCK2, RAO to RA9, CASO to CAS1, RASO to RAS2, LWE , RA9, RASO, RAS1, RAS2, CASO, CAS 1, ÃE, UWE, LWE WOBBLE, BIDATA, BICLK WRITE, SSP2/1, RAPC, WAPC , I VCO control voltage 84 R I VCO bias resistor connection 85 PD 0 Charge , 193 Unused NC 192 Unused 194 RASO O 195 RAS1 O 196 RAS2 O , pull-up resistors. RAO to RA9 (output) Buffer RAM address lines. LC898023K RASO, RAS1, RAS2 -
OCR Scan
Abstract: ) . PCK2, RAO to RA9, CASO to CAS1, RASO to RAS2, LWE, UWE, OE, SUBSYNC (9 ) . PDS1 to PDS3 , , C/D, ACK, ATN RD, WR, SUAO to SUA7, CS DO to D7 IOO to 1015 RAO to RA9, RASO, R A Sl, RAS2, CASO , tied to Vss- 83 VC NT I VCO control voltage 84 R I VCO bias resistor connection , Unused 193 NC Unused 194 RASO 195 RAS1 0 196 RAS2 0 197 LWE 0 , pull-up resistors. RAO to RA9 (output) Buffer RAM address lines. LC898023 RASO, RAS1, RAS2 (output -
OCR Scan

qml-38535

Abstract: 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC = No connection Q Terminal symbol RAS2 RAS3 RASI RSEL0 RSEL1 CASO CASI CLR TC VCC A15 O7 A7 A14 O6 MSEL A6 A13 O5 A5 A12 O4 U Terminal symbol RAS2 RAS3 RASI , RASI H L H L L L L RSEL1 X X X L L H H RSEL0 X X X L H L H RAS0 H L H L H H H RAS1 H L H H L H H RAS2 H , refresh Terminal count for 128 line refresh Function * - Through 1k resistor. FIGURE 2. Truth tables , resistor, the terminal count output, TC, will go low every 128 counts (for 16k RAMs) instead of every 256
DEPARTMENT OF DEFENSE
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qml-38535 3V146 MIL-PRF-38535 5962-E087-08 MIL-STD-883 MIL-HDBK-103 QML-38535

DD15

Abstract: LC898093 ) · · · · · · RA0 to RA9, CAS0 and CAS1, RAS0 to RAS2, LWE, UWE, OE, SSP2/1, RAPC, WAPC, H11T0, LDH , , SUA0 to SUA7, CS D0 to D7 IO0 to IO15 RA0 to RA9, RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE WOBBLE , bias resistor connection Write strategy analog signals Microcontroller data signal lines These , O 195 RAS1 O 196 RAS2 O 197 LWE O DRAM lower write enable 198 , lines. RAS0, RAS1, RAS2 (output) Buffer DRAM RAS outputs. Normally, RAS0 is used. However, if two 16
SANYO Electric
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DD15 SQFP208

DIMM 72 pin out

Abstract: each bank are dotted. Banks are divided into words, 0 and 2, selectable by RASO and RAS2 on the first , NC DQ10 DQ12 DQ14 A7 Vcc A9 RÂS2 NC DQ19 CASO CÂS3 RASO A12 A13 DQ21 DQ23 DQ25 DQ27 DQ29 DQ30 DQ32 DQ34 PD2 PD4 PD6 V ss Back Side X 36 DQO DQ2 DQ4 DQ6 Vcc AO A2 A4 A6 PQ8 DQ10 DQ12 DQ14 A7 Vcc A9 RÂS2 , detect outputs must be tied to V cc through a pullup resistor to generate a high-logic level when the SO
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OCR Scan
DIMM 72 pin out AO-A11
Abstract: to RAS2, LWE, UWE, OE, SSP2/1, RAPC, WAPC, HI 1T0, LDH, ATEST3/1, WDAT, NWDAT, EFMG, SHOCK, LOCK , RD, WR, SUAO to SUA7, CS DO to D7 IOO to 1015 RAO to RA9, RASO, R A S1, RAS2, CASO, CAS 1, OE, UWE , voltage 84 R I VCO bias resistor connection PD 0 Charge pump output Analog system , RAS1 O 196 RAS2 O 197 lW Ã' O Digital system power supply (5 V) Pin No , pins have built-in pull-up resistors. RAO to RA9 (output) Buffer RAM address lines. RASO, RAS1, RAS2 -
OCR Scan

a13483

Abstract: A1348 ) · · · · · RA0 to RA9, CAS0 to CAS1, RAS0 to RAS2, LWE, UWE, OE [INOUT] (13) · · · · · D0 to D7 , SUA7, CS D0 to D7 IO0 to IO15 RA0 to RA9, RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE WOBBLE, BIDATA , R I VCO bias resistor connection 85 PD O Charge pump output 86 VDD P , 196 RAS2 O DRAM RAS signal outputs 197 LWE O DRAM lower write enable 198 , ) Buffer RAM address lines. RAS0, RAS1, RAS2 (output) Buffer DRAM RAS outputs. Normally, RAS0 is used
SANYO Electric
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a13483 A1348 LC898023KW 898023KL

DIMM 72 pin out

Abstract: ms6464 words, 0 and 2, selectable by RASP and RAS2 on the first bank, and if so equipped, RAS1 and RAS3 on the , DQ12 DQ14 A7 V cc A9 RAS2 NC DQ19 CÂS0 CAS3 RASO A12 A13 DQ21 DQ23 DQ25 DQ27 DQ29 DQ30 DQ32 DQ34 PD2 PD4 PD6 Vcc A9 RAS2 PQ17 DQ19 CASO CAS3 RASO A12 A13 DQ21 DQ23 DQ25 DQ27 DQ29 DQ30 DQ32 DQ34 , through a pullup resistor to generate a high-logic level when the SO DIMM PD pin is open or low-voltage
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OCR Scan
ms6464
Abstract: , NWDAT (8) · · · · · · PCK2, RA0 to RA9, CAS0 to CAS1, RAS0 to RAS2, LWE, UWE, OE, SUBSYNC (9) · · · · , , RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE WOBBLE, BIDATA, BICLK WRITE, SSP2/1, RAPC, WAPC, H11T0 , voltage VCO bias resistor connection Microcontroller data signal lines These pins have built-in , Unused 194 RAS0 O 195 RAS1 O 196 RAS2 O 197 LWE O DRAM lower write , ) Buffer RAM address lines. No. 6494-9/12 LC898023 RAS0, RAS1, RAS2 (output) Buffer DRAM RAS outputs SANYO Electric
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CRYSTAL 20 mhZ 4 pins

Abstract: Electronic micro servo , NWDAT (8) · · · · · · PCK2, RA0 to RA9, CAS0 to CAS1, RAS0 to RAS2, LWE, UWE, OE, SUBSYNC (9) · · · · , , RAS0, RAS1, RAS2, CAS0, CAS1, OE, UWE, LWE WOBBLE, BIDATA, BICLK WRITE, SSP2/1, RAPC, WAPC, H11T0 , voltage VCO bias resistor connection Microcontroller data signal lines These pins have built-in , NC Unused 194 RAS0 O 195 RAS1 O 196 RAS2 O 197 LWE O DRAM , resistors. RA0 to RA9 (output) Buffer RAM address lines. No. 6614-9/12 LC898023K RAS0, RAS1, RAS2
SANYO Electric
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CRYSTAL 20 mhZ 4 pins Electronic micro servo a1318 EFMG
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