NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| CA3338AMZ96 | Intersil Corporation | DAC 1-CH R-2R 8-Bit 16-Pin SOIC W T/R | 
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| CA3338MZ96 | Intersil Corporation | DAC 1-CH R-2R 8-Bit 16-Pin SOIC W T/R |
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| MX7524JN+2 | Maxim Integrated Products | DAC 1-CH R-2R 8-Bit 16-Pin PDIP N, Rail / Tube |
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| MX7228UQ/883B | Maxim Integrated Products | DAC 8-CH R-2R 8-Bit 24-Pin CDIP N, Bulk |
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| MX7228TQ/883B | Maxim Integrated Products | DAC 8-CH R-2R 8-Bit 24-Pin CDIP N, Bulk |
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| Part | Manufacturer | Description | Type | Ordering |
| R2RP429 | Interconnect Devices | Crimp Contact: 34.52: F: 1.8: Gold |
1 pages, |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: R-2R Ladder Network R-2R Series · ±2% Absolute tolerance · Ladder accuracy +/- 1 LSB · 8 and 10 bit R-2R Schematic · QSOP Package - Small Footprint · Standard Sn/Pb and Pb-free terminations , R R 1 2R 2 3 15 R R 2R 2R 16 R R 2R 2R 4 14 5 R 2R 6 12 13 11 R 2R 2R 7 2R 9 8 2R R 2R 10 QS009 QS009 20-Pin,10 bit, R-2R Schematic 16 15 R 14 R 1 2 R R 2R 2R 2R 3 ... | Original |
2 pages, |
12 bit r2r ladder 2r 55 a r2r ladder 14 pin 6 bit r2r ladder r2r ladder 10 pin r2r ladder network r2r ladder 16 bit ladder network r2r 10k ladder network r2r ladder datasheet abstract |
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| Abstract: 1 megohm For information on R/2R Thick Film Networks, download Bourns' R/2R Application Note. , "Termination" option) R/2R Series Thick Film Networks Product Characteristics Resistance Range Models 4100 , Circuit 11 RT 9 10 R R R R R R 2R 2R 2R 2R 2R RT 16 16-PIN 16-PIN 8-BIT DIP 2R R 2R How To Order 4116R 4116R - R2R - 501 _ See applicable model data sheet , 13 12 11 OUT 9 10 R R R R R R 2R 2R R 2R 2R 2R 2R ... | Original |
1 pages, |
4600X 4100R 4114R lf 4116R lf pin outs 4300R 4600H 4600M 10-PIN 4116R 4116R lf datasheet abstract |
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| Abstract: External dimensions (Unit : mm) Features 1) 8bit 12-channel D/A converters adopting R-2R system. 2 , Please set to VCC VDD. 1/2 BH2221FV BH2221FV Standard ICs Block diagram 1 20 GND 3 R-2R DAC AO5 4 R-2R DAC 8bitREG + DEC AO6 5 R-2R DAC 8bitREG + DEC AO7 6 R-2R DAC 8bitREG + DEC AO8 7 R-2R DAC 8bitREG + DEC AO9 8 R-2R DAC 8bitREG + DEC AO10 9 VDD 10 VCC VCC 19 AO2 R-2R DAC 18 AO1 16 CLK Serial ... | Original |
2 pages, |
SSOP-B20 BH2221FV AO11 BH2221FV abstract |
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| Abstract: MODELS 898, 899 R/2R Ladder Dual-In-Line Thick Film Resistor Networks ELECTRICAL Standard , R 2R 2R 2R 2R 2R R R R 2R 2R R 2R 2R R R R 2R 2R 2R 2R 2R R R R 2R 2R 2R 2R 1 1 899-10 Circuit 10 Bits, 14 Leads 14 2R 2R 2R R R R R R 2R 2R 2R 2R 2R R R R 2R R 2R 2R 1 Note: Custom , 70°C STANDARD RESISTANCE VALUES, OHMS R/2R 10K/20K 10K/20K R/2R 25K/50K 25K/50K 50K/100K 50K/100K Model 898-8X 898-8X ... | Original |
3 pages, |
R10K MIL-R-83401 898-81-R10K 898 resistor network datasheet abstract |
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| Abstract: R/2R Ladder Networks R/2R Ladder Networks are available in both DIP and SIP (Molded or Conformal , R 2R 2R 2R 2R 2R Standard R/2R Ladder Networks have a resistance tolerance of �0% (�0% available on all but low profile SIPs). 2R R 2R 2R Standard R/2R Ladder Networks , 2 3 4 5 6 7 8 LSB 10-PIN 10-PIN 8-BIT SIP PIN 1 R R R R R 2R 2R 2R 2R 2R 2R SIP-CONFORMAL 14 Pin - 7 Bit 16 Pin - 8 Bit R 2R BIT OUT ... | Original |
1 pages, |
RESISTOR SIP 9 resistor network DIP 10-PIN r2r ladder network 12 bit r2r ladder "resistor networks" dip 14 r2r resistor ladder r2r ladder 10 pin analog to digital r2r ladder ladder network SIP 9 Resistor r2r ladder 10 pin 16-PIN 16-PIN abstract |
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| Abstract: adopting R-2R system. 2) 3-wire + 1-wire 16-bit serial interface. 3) POWER ON RESET circuit. 4) The full , DEC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8 8bitREG + DEC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R ... | Original |
3 pages, |
Vdd-2 AO16 SsOP-b28 package SSOP-B28 ao13 AO11 BH2222FV BH2222FV abstract |
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| Abstract: Features 1) 8bit 10-channel D/A converters adopting R-2R system. 2) 3-wire 12-bit serial interface. 3 , AO5 4 R-2R DAC 8bitREG + DEC AO6 5 R-2R DAC 8bitREG + DEC AO7 6 R-2R DAC 8bitREG + DEC AO8 7 R-2R DAC 8bitREG + DEC AO9 8 R-2R DAC 8bitREG + DEC VCC VCC 8bitREG + DEC 15 AO1 VCC R-2R DAC R-2R DAC 14 DI , 8bitREG + DEC R-2R DAC 10 AO10 VCC R-2R DAC VCC 2 VCC AO3 16 GND VCC ... | Original |
2 pages, |
SSOP-B16 BH2223FV BH2223FV abstract |
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| Abstract: , providing added chip capacity. It is a good choice for a 14 bit R/2R ladder of R = 5K. Select Model 1460 , R/2R LADDER 11 10 Ground Out 18 17 16 15 14 13 12 11 10 R R R R R R 2R R R 2R 2R 2R 2R 2R 2R 2R 18 2 17 3 5 6 7 8 16 14 13 12 4 15 R R R R 2R 2R 2R 2R 2R 2R 2R 2R 1 1 R 2 3 4 5 6 7 8 9 9 R/2R LADDER 11 10 Ground Out 18 17 16 15 14 13 12 11 10 R R ... | Original |
1 pages, |
datasheet abstract |
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| Abstract: Model TxxS Vishay Techno Single-In-Line, Coated, 4 Bits to 8 Bits R/2R Ladder Networks APPLICATIONS R/2R Ladder networks for D/A and A/D converter with bi-polar or CMOS switches. ELECTRICAL , , 25 kilohms, 50 kilohms and 100 kilohms. SCHEMATIC n Bits: n = 4 thru 8 R 2R 1 GRD 2R 2 Bn (LSB) R R 2R 3 Bn-1 R 2R R R 2R 4 Bn-2 2R n-1 B3 , signifies number of zeros to follow. EXAMPLE: 104 = R = 100 kilohms. REFERENCE: 2R = 200 kilohms. ... | Original |
1 pages, |
ladder network datasheet abstract |
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| Abstract: MICRO-DAC DAC CMOS DAC DAC CMOS MICRO-DAC Fig. 2 R-2R AC DAC DAC DAC RfB D 0 10nA R-2R VREF D 2 - 1 MICRO-DAC 15k IOUT2 8 DAC R-2R 1 I I OUT1 OUT2 D/A CMOS DAC DAC 2 , MICRO-DAC VREF 15k R 2R Fig. 5 IOUT1 R-2R VREF 10 DAC 3V 8 DAC 5V , ://www.national.com DAC Fig. 7DAC R-2R 15k DAC RfB DAC Fig. Ã- 1 ... | Original |
12 pages, |
LM363 AN-271 DAC1208 LF351 LF351 APPLICATION LM11 LM11 national LM143 LM319 ADC0801 DAC1230 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| label without a colon began a line, and the operands ; started with a non-numeric character. L$1 add %< L$2: add %< L$3 add %< L$4 add 2,%r2,%r2 L$5: add 2,%r2,%r2 L$6 add 2,%r2,%r2 ; An instruction or pseudo-op may begin anywhere after column 0. b,n label_without_colon www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |
| .text .align 0 smull r0, r1, r2, r3 umull r0, r1, r2, r3 smlal r0, r1, r2, r3 umlal r0, r1, r4, r3 smullne r0, r1, r3, r4 smulls r1, r0, r9, r11 umlaleqs r2, r9, r4, r9 smlalge r14, r10, r8, r14 www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |
| . // //////////////////////////////////////////////////////////////////////////// *F*/ void IDct_AAN(short *coef_block) { int r0, r1, r2, r3, r4, r5, r6, r7, tmp, i; short + ) { r0 = lptr[40]; r1 = lptr[24]; r2 = r0 - r1; r3 = r0 + r1; r0 = lptr[8]; r1 = lptr[56]; r4 = r0 + r1; r0 = r0 - r1; r1 = SCALEM(b5*(r2-r0); r0 = SCALEM(b4*r0) - r1; r2 = r1 - SCALEM(b2*r2); r1 = r4 - r3; r4 = r4 + r3; r5 = r0 - r4; r6 = SCALEM(b3*r1) - r5; r7 = r6 + r2; r0 = lptr[0]; r1 = lptr[32]; r2 = r0 + r1; r3 = r0 - r1; r0 www.datasheetarchive.com/download/67622953-279967ZC/timedc~1.zip (aan_idct.cpp) |
Intel | 04/05/1998 | 131.9 Kb | ZIP | timedc~1.zip |
| . // //////////////////////////////////////////////////////////////////////////// *F*/ void IDct_AAN(short *coef_block) { int r0, r1, r2, r3, r4, r5, r6, r7, tmp, i; short + ) { r0 = lptr[40]; r1 = lptr[24]; r2 = r0 - r1; r3 = r0 + r1; r0 = lptr[8]; r1 = lptr[56]; r4 = r0 + r1; r0 = r0 - r1; r1 = SCALEM(b5*(r2-r0); r0 = SCALEM(b4*r0) - r1; r2 = r1 - SCALEM(b2*r2); r1 = r4 - r3; r4 = r4 + r3; r5 = r0 - r4; r6 = SCALEM(b3*r1) - r5; r7 = r6 + r2; r0 = lptr[0]; r1 = lptr[32]; r2 = r0 + r1; r3 = r0 - r1; r0 www.datasheetarchive.com/download/26124066-227657ZC/timedc~1.zip (aan_idct.cpp) |
Intel | 04/05/1998 | 131.9 Kb | ZIP | timedc~1.zip |
| . // //////////////////////////////////////////////////////////////////////////// *F*/ void IDct_AAN(short *coef_block) { int r0, r1, r2, r3, r4, r5, r6, r7, tmp, i; short + ) { r0 = lptr[40]; r1 = lptr[24]; r2 = r0 - r1; r3 = r0 + r1; r0 = lptr[8]; r1 = lptr[56]; r4 = r0 + r1; r0 = r0 - r1; r1 = SCALEM(b5*(r2-r0); r0 = SCALEM(b4*r0) - r1; r2 = r1 - SCALEM(b2*r2); r1 = r4 - r3; r4 = r4 + r3; r5 = r0 - r4; r6 = SCALEM(b3*r1) - r5; r7 = r6 + r2; r0 = lptr[0]; r1 = lptr[32]; r2 = r0 + r1; r3 = r0 - r1; r0 www.datasheetarchive.com/download/14922601-227643ZC/timedc~1.zip (aan_idct.cpp) |
Intel | 04/05/1998 | 131.9 Kb | ZIP | timedc~1.zip |
| or #H'80,r0 mov.l @(r0,r2),r3 mov.l r3,@(r0,r1) mov r4,r0 ;cpu addr err or #H'24,r0 mov.l @(r0,r2),r3 mov.l r3,@(r0,r1) mov r4,r0 ;ill slot or #H'18,r0 mov.l @(r0,r2),r3 mov.l r3,@(r0,r1) mov r4,r0 ;ill inst or #H'10,r0 mov.l @(r0,r2),r3 mov.l r3,@(r0,r1) mov r4,r0 ;nmi or #H'2c,r0 mov.l @(r0,r2),r3 mov.l r3,@(r0,r1) mov r4,r0 ;User brk or #H'30,r0 mov.l @(r0,r2),r3 mov.l r3,@(r0,r1) mov r4,r0 ;sci0 err or #H'C8,r0 rotl r0 rotl r0 mov.l @(r0 www.datasheetarchive.com/download/55747878-691915ZC/app9410.zip (Copyvect.src) |
Renesas | 04/02/2005 | 354.36 Kb | ZIP | app9410.zip |
| 2 moveq r2, r3 movne r4, r5 movlt r6, r7 movge r8, r9 movle r10, r11 movgt r12, r13 movcc r1 movls r15, r14 movhs r9, r8 movul r1, r3 movs r0, r8 movuls r0, r7 add r0, r1, #10 add r2, r3, r4 add r5, r6, r7, asl #5 add r1, r2, r3, lsl r1 and r0, r1, #10 and r2, r3, r4 and r5, r6, r7, asl #5 and r1, r2, r3, lsl r1 eor r0, r1, #10 eor r2, r3, r4 eor r5, r6, r7, asl #5 eor r1, r2, r3, lsl r1 sub r0, r1, #10 sub r2, r3, r4 sub r5, r6, r7, asl #5 sub r1, r2, r3, lsl r1 adc r www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |
| , r0 movs r2, r1 ldreq r2, =ExecuteArmTest ldrne r2, =ExecuteThumbTest bic r2, r2, #3 ldr r3, =Execute cmp r2, r3 blo CopyTest_loop ;- Test Arm or Thumb Call requested movs r2, r1 beq ArmCall ;- Thumb Call add r4, r4, #1 ;- Wait push button released ExitLoop ldr r2, [r0, #PIO_PDSR] ands www.datasheetarchive.com/download/80887645-39381ZC/at91libv2.zip (eb40_x40_test.s) |
Atmel | 16/05/2001 | 1258.04 Kb | ZIP | at91libv2.zip |
| , r0 movs r2, r1 ldreq r2, =ExecuteArmTest ldrne r2, =ExecuteThumbTest bic r2, r2, #3 ldr r3, =Execute cmp r2, r3 blo CopyTest_loop ;- Test Arm or Thumb Call requested movs r2, r1 beq ArmCall ;- Thumb Call add r4, r4, #1 ;- Wait push buuton released ExitLoop ldr r2, [r0, #PIO_PDSR] ands www.datasheetarchive.com/download/80887645-39381ZC/at91libv2.zip (eb63_execute.s) |
Atmel | 16/05/2001 | 1258.04 Kb | ZIP | at91libv2.zip |
| refresh */ ldr r0, DRFPR ldr r1, drfpr_val str r1, [r0] /* * SYSCON2: clear bit 2, DRAM is 32 bits wide */ ldr r0, SYSCON2 ldr r2, [r0] ldr r1, syscon2_mask bic r2, r2, r1 str r2, [r0 Bit, 5 Waitstates * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates */ ldr r0, MEMCFG1 ldr r1, memcfg1_val str r1, [r0] /* * MEMCFG2 * Setting up ? with 0 * */ ldr r0, MEMCFG2 ldr r2, [r0] ldr r1, memcfg2_mask bic r2, r2, r1 ldr r1, memcfg2_val orr r2, r2, r1 str r2, [r0 www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (memsetup.S) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |