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quad time delay

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 1.5 - 2.5 , TSLEW - 4.0 - 4.5 - 5.0 - 5.5 ns Time Adders Slew-rate limited delay , for extended periods of time may affect device reliability. Recommended Operation Conditions , 6.0 - 8.0 - 10.0 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - 0 - ns GCK to output ... Xilinx
Original
datasheet

10 pages,
176.81 Kb

XC95108-10TQG100C XC95108-15PC84C XC95108-15PQ100C XC95108-15PQG100I XC95108-20PCG84C XC95108-20PQG100C PQ100 PC84 84-Pin Plastic Leaded Chip Carrier PQG160 xc95108 tq100 XC95108-7PQG160C XC95108-10PCG84I XC95108-10PQG100C XC95108 XC95108-20PQG160I XC95108 XC95108-15TQ100I XC95108 XC95108-10PQG160I XC95108 XC95108-15TQG100C XC95108 XC95108-20TQ100I XC95108 XC95108 XC95108 XC95108-15PCG84C TEXT
datasheet frame
Abstract: Delays Combinatorial logic propagation delay Register setup time Register hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal , conditions for extended periods of time may affect device reliability. Recommended Operation Conditions , to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter , internal operating frequency TPSU TPH TPCO TOE TOD TPOE TPOD TWLH TAPRPW I/O setup time before p-term clock ... Xilinx
Original
datasheet

10 pages,
109.02 Kb

XC95108-20PQG160I XC95108-15PC84C TQG100 PGC84 xc95108-10pqg100i XC95108-10PQ160C XC95108 TEXT
datasheet frame
Abstract: Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay , implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device , TPLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time ... Xilinx
Original
datasheet

10 pages,
184.32 Kb

XC9572XL-5VQG44C XC9572XL-5PCG44C XC9572XL TQG100 xc9572xl pin configuration xc9572xl pin TQFP 144 PACKAGE footprint DS058 XC9572XL-10VQG44I xc9572xl XC9572XL TEXT
datasheet frame
Abstract: propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay Register async , extended periods of time may affect device reliability. 3. For soldering guidelines and thermal , output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term ... Xilinx
Original
datasheet

10 pages,
190.26 Kb

XC9572XL-7VQG64I XC9572XL-10CS48C VQ64 xc9572xl-10vqg44c XC9572XL-10VQG64I XC9572XL-5PCG44C XC9572XL-5VQG44C XC9572XL-10TQG100C xc9572xl pin XC9572XL-10-TQ100 XC9572XL-10TQG100I xc9572xl XC9572XL-10VQG44I XC9572XL XC9572XL TQG100 XC9572XL xc9572xl pin configuration XC9572XL XC9572XL XC9572XL TEXT
datasheet frame
Abstract: Combinatorial Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 2.3 - , valid time - 0.4 - 0.5 - 1.0 ns TAOI Register async. S/R to output delay - , CONNECT II feedback delay Time Adders TPTA TSLEW DS057 DS057 (v1.8) July 15, 2005 Product Specification , implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device , valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ... Xilinx
Original
datasheet

10 pages,
190.37 Kb

XC9572XL-7VQG64C XAPP427 XC9500XL XC9572 XC9572XL 7TQ100I XC9572XL-10 XC9572XL-10TQ100I XC9572XL-10VQ44I XC9572XL-5 XC9572XL-5VQ44C XC9572XL-5VQG44C XC9572XL-7 XC9572XL-7PCG44C XAPP114 XC9572XL xc9572xl pin configuration XC9572XL XC9572XL XC9572XL TEXT
datasheet frame
Abstract: Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 2.3 - 2.6 , delay Time Adders TPTA TSLEW DS057 DS057 (v2.0) April 3, 2007 Product Specification www.xilinx.com , to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3 , time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ns GCK to output , - 178.6 - 125.0 - 100.0 MHz TPSU I/O setup time before p-term clock input ... Xilinx
Original
datasheet

10 pages,
184.78 Kb

XC9500XL XILINX XC9572XL-10CS48C XC9572XL-10 XC9572XL-10PC44I XC9572XL-10PCG44C XC9572XL-10TQ100C XC9572XL-10TQG100C XC9572XL-10VQ64I XC9572XL-5VQG44C XC9572XL-5 XC9572XL-10VQG64I XC9572XL-10PC44C XC9572XL-10CS48I XC9572XL XC9572XL-10VQG44C XC9572XL XC9572XL-5TQG100C XC9572XL xc9572xl-10PCG44C pin XC9572XL XC9572XL-7TQ100C XC9572XL XC9572XL-7PCG44C XC9572XL XC9572XL XC9572XL xc9572xl pin configuration TEXT
datasheet frame
Abstract: Cload 1ns Rise and Fall Time Mismatch 1.5ns Prop Delay Mismatch Low Quiescent Current, , , tF Mismatch CL = 1000pF 0.5 ns tD-1 Turn-Off Delay Time CL = 1000pF 12.5 ns tD-2 Turn-On Delay Time CL = 1000pF 14.5 ns tDdelta tD-1 - TD-2 Mismatch CL = 1000pF 2 ns tRFdelta Tenable Enable Delay Time 12 ns Tdisable Disable Delay , = 1000pF 1 tD-1 Turn-Off Delay Time CL = 1000pF 11.5 ns tD-2 Turn-On Delay ... Elantec
Original
datasheet

12 pages,
122.59 Kb

ultrasonic transducer drive circuits MDP0040 EL7457CU EL7457CS EL7457C TEXT
datasheet frame
Abstract: Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 1.5 - 2.5 , Time Adders TPTA(1) Incremental product term allocator delay - 1.0 - 1.0 - 1.0 , Absolute Maximum Ratings conditions for extended periods of time may affect device reliability , 6.0 - 8.0 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ns GCK to output valid - 4.5 - ... Xilinx
Original
datasheet

10 pages,
174.9 Kb

XC95144 Family XC9500 XC95144-10TQ100I TQ100 XC95144-15-PQ160 XC95144-15PQ100C XC95144-15PQG100C PQ160 XC95144-10PQ100I XC95144-7PQG160C XC95144 PQ100 XC95144-15pqg160i xc95144-15pqg100i XC95144 XC95144-15PQG160C XC95144 XC95144-10TQG100I XC95144 xc9514415pqg160i XC95144 Plastic Quad Flat Pack PQFP XC95144 XC95144-10PQG160C XC95144 XC95144-10PQG100I XC95144 XC95144 XC95144 TEXT
datasheet frame
Abstract: setup time Register hold time Register clock to output valid time Register async. S/R to output delay , delay) 15 ns 15 ns Pkg. Symbol PQ160 PQ160 No. of Pins 160-pin Package Type Plastic Quad Flat Pack , conditions for extended periods of time may affect device reliability. Recommended Operation Conditions , Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O ... Xilinx
Original
datasheet

10 pages,
91.65 Kb

XCN11010 XC95144-15TQ100C XC95144-15PQ100C Plastic Quad Flat Pack PQFP XC95144-15TQG100I XC95144-15PQ160C XC95144 PQG100 XC95144 TEXT
datasheet frame
Abstract: TF Fast CONNECT II feedback delay Time Adders TPTA TSLEW DS057 DS057 (v1.6) September 15, 2004 , for extended periods of time may affect device reliability. 3. For soldering guidelines and thermal , XC9572XL-7 XC9572XL-7 - 4.8 - 6.5 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ns GCK to output valid - , - 125.0 - 100.0 MHz TPSU I/O setup time before p-term clock input 1.7 - ... Xilinx
Original
datasheet

10 pages,
190.8 Kb

84 PLCC pin configuration XAPP114 XC9500XL XC9572 XC9572XL-10 XC9572XL-10CS48I XC9572XL-10TQ100C XC9572XL-10VQ44 XC9572XL-5 XC9572XL-5TQ100C XC9572XL-7VQ44I XC9572XL-7 XC9572XL-7CSG48C XC9572XL XC9572XL-7TQ100I XC9572XL XC9572XL-7TQG100C XC9572XL XAPP427 XC9572XL 44 VQFP package XC9572XL XC9572XL-5VQG44C XC9572XL XC9572XL XC9572XL xc9572xl pin configuration TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
No abstract text available
/download/51876408-957198ZC/x80140_customer.zip ()
Xicor 24/01/2003 1066.09 Kb ZIP x80140_customer.zip
Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors FEATURES • Quad voltage Monitor and Sequencing -Four independent voltage monitors -Four time delay circuits -Remote delay via SMBus -Programmable voltage thresholds and delay times -Sequence up to interface • Available packages -20-lead Quad No-Lead Frame (QFN - 5 x 5 mm) APPLICATIONS • General Purpose Timers • Long Time Delay Generation • Cycle Timers / Waveform Generation •
/datasheets/files/xicor/www.xicor.com/folders/x80140.html
Xicor 07/02/2003 31.6 Kb HTML x80140.html
reset delay time is adjustable using an external capacitor and the manual reset input may be used with a program pin. The preset voltage thresholds are accurate to ±1.5% over temperature. The reset delay time preset voltage thresholds are accurate to ±1.5% over temperature. The reset delay time is adjustable temperature. The reset delay time is adjustable using an external capacitor and the manual reset input may over temperature. The reset delay time is adjustable using an external capacitor and the manual
/datasheets/files/linear/c1003/c1144/c1043/c1124/p2261/p2261-variations-v1.html
Linear 09/02/2007 13.83 Kb HTML p2261-variations-v1.html
Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors FEATURES • Quad voltage Monitor and Sequencing -Four independent voltage monitors -Four time delay circuits -Remote delay via SMBus -Programmable voltage thresholds and delay times -Sequence up to interface • Available packages -20-lead Quad No-Lead Frame (QFN - 5 x 5 mm) APPLICATIONS • General Purpose Timers • Long Time Delay Generation • Cycle Timers / Waveform Generation •
/datasheets/files/xicor/www.xicor.com/folders/x80142.html
Xicor 07/02/2003 31.6 Kb HTML x80142.html
Single SVS With Pgmmable UV Threshold & Reset Time Delay TL7702B TL7702B Single SVS With Pgmmable UV Threshold & Reset Time Delay TL7705A TL7705A Single Supply Voltage Supervisor for 5V Systems with Programmable Time Delay TL7705B TL7705B Single Supply Voltage Supervisor ror 5V Systems with Programmable Time Delay TL7709A TL7709A Single SVS For 9v Systems W/Pgmmable Time Delay TL7712A TL7712A Single SVS For 12V Systems W/Pgmmable Time Delay TL7726 TL7726
/datasheets/files/texas-instruments/docs/html/tables/products_by_name_7.html
Texas Instruments 09/07/2002 349.69 Kb HTML products_by_name_7.html
Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors FEATURES • Quad voltage Monitor and Sequencing -Four independent voltage monitors -Four time delay circuits -Remote delay via SMBus -Programmable voltage thresholds and delay times -Sequence up to interface • Available packages -20-lead Quad No-Lead Frame (QFN - 5 x 5 mm) APPLICATIONS • General Purpose Timers • Long Time Delay Generation • Cycle Timers / Waveform Generation •
/datasheets/files/xicor/www.xicor.com/folders/x80121.html
Xicor 07/02/2003 31.6 Kb HTML x80121.html
ps. The driver's typical propagation delay time is 1.7 ns, while the receiver's typical propagation delay time is 1.4 ns. Both drivers and receivers are characterized for operation in industrial The new revised data sheets show the minimum and maximum propagation delay time of the drivers as well as the receivers. The driver's propagation delay time has a minimum of 1 ns and a maximum of 2.5 ns. The receiver's propagation delay time has a minimum of 1.4 ns and a maximum of 4.1 ns. These
/datasheets/files/texas-instruments/data/sc/docs/msp/showcase/vol28/page06.htm
Texas Instruments 08/02/1999 19.38 Kb HTM page06.htm
Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors FEATURES • Quad voltage Monitor and Sequencing -Four independent voltage monitors -Four time delay circuits -Remote delay via SMBus -Programmable voltage thresholds and delay times -Sequence up to interface • Available packages -20-lead Quad No-Lead Frame (QFN - 5 x 5 mm) APPLICATIONS • General Purpose Timers • Long Time Delay Generation • Cycle Timers / Waveform Generation •
/datasheets/files/xicor/www.xicor.com/folders/x80133.html
Xicor 07/02/2003 31.6 Kb HTML x80133.html
Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors FEATURES • Quad voltage Monitor and Sequencing -Four independent voltage monitors -Four time delay circuits -Remote delay via SMBus -Programmable voltage thresholds and delay times -Sequence up to interface • Available packages -20-lead Quad No-Lead Frame (QFN - 5 x 5 mm) APPLICATIONS • General Purpose Timers • Long Time Delay Generation • Cycle Timers / Waveform Generation •
/datasheets/files/xicor/www.xicor.com/folders/x80120.html
Xicor 07/02/2003 31.6 Kb HTML x80120.html
Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors FEATURES • Quad voltage Monitor and Sequencing -Four independent voltage monitors -Four time delay circuits -Remote delay via SMBus -Programmable voltage thresholds and delay times -Sequence up to interface • Available packages -20-lead Quad No-Lead Frame (QFN - 5 x 5 mm) APPLICATIONS • General Purpose Timers • Long Time Delay Generation • Cycle Timers / Waveform Generation •
/datasheets/files/xicor/www.xicor.com/folders/x80130.html
Xicor 07/02/2003 31.6 Kb HTML x80130.html