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pt36C* Datasheet

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PT36CB010 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
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PT36CB020 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
53.91 Kb

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PT36CB030 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
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PT36CB050 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
53.91 Kb

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PT36CB100 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
53.91 Kb

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PT36CB150 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
53.91 Kb

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PT36CB200 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
53.91 Kb

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PT36CB400 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
53.91 Kb

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PT36CB500 Kappa Technologies, Inc. 3-BIT PROGRAMMABLE DELAY LINE
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1 pages,
53.91 Kb

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pt36C*

Catalog Datasheet Results Type PDF Document Tags
Abstract: Preliminary Data Sheet August 2000 ORCA® Series 4 Field-Programmable Gate Arrays Programmable Features s High-performance platform design. - 0.13 µm seven-level metal technology. - Internal performance of >250 MHz (four logic levels). - I/O performance of >416 MHz for all user I/Os. - Over 1.5 million usable system gates. - Meets multiple I/O interface standards. - 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. - Embedded block RAM (EBR) f ... Original
datasheet

132 pages,
1300.12 Kb

21-INPUT pin diagram of ic 7495 shift register CORE F5A datasheet abstract
datasheet frame
Abstract: PT36CB010 PT36CB020 PT36CB030 1 ns ± .4 ns 2 ns ± .4 ns 3 ns ± .5 ns 7 ns 14 ns 21 ns PT36CB050 PT36CB100 PT36CB150 5 ns ± .6 ns 10 ns ±1.0 ns 15 ns ±1.3 ns 35 ns 70 ns 105 ns PT36CB200 PT36CB400 PT36CB60- 20 ns , TEST CONDITIONS PT36CB010 KAPPA (DATE CODE) .400 (10.1) MAX I ein TRI Tw Pulse Voltage Pulse ... OCR Scan
datasheet

1 pages,
53.91 Kb

PT36CB400 PT36CB020 PT36CB050 PT36CB100 PT36CB150 PT36CB200 PT36 PT36CB030 PT36CB010 pt36C datasheet abstract
datasheet frame
Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features ­ 1 to 7.8 Mbits memory ­ True Dual Port/Pseudo Dual Port/Single Port ­ Dedicated FIFO logic for all block RAM ­ 500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... Original
datasheet

243 pages,
1343.14 Kb

umi u26 SCM15 SC80 SC40 SC25 SC15 SC115 426 b34 transistor pt42c transistor pt36c pt36C DS1004 DS1004 abstract
datasheet frame
Abstract: Data Sheet January 15, 2002 ORCA® Series 4 FPGAs Introduction Traditional I/O selections: - LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os. - Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. - Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. - Two slew rates supported (fast and slew-limited). - Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time a ... Original
datasheet

174 pages,
880.2 Kb

K72 R8 CE1M K72 R1 CORE F5A INTEL Core i7 860 K72 v4 datasheet transistor pt36C transistor pt42c transistor pt36c datasheet abstract
datasheet frame
Abstract: ORCA® ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on ... Original
datasheet

242 pages,
1154.54 Kb

pt36C l200c transistor pt42c L200C equivalent datasheet abstract
datasheet frame
Abstract: M PT-8C MPT-10C MPT-10C MPT-12C MPT-12C MPT-15C MPT-15C MPT-18C MPT-18C M PT-22C PT-22C M PT-36C M PT-45C PT-45C 8.0 10.0 12.0 15.0 18.0 22.0 36.0 ... OCR Scan
datasheet

2 pages,
169.17 Kb

pt8c pt36c datasheet abstract
datasheet frame
Abstract: Data Addendum March 2002 ORCA® OR3LxxxB Series Field-Programmable Gate Arrays Introduction Features High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply voltage for speed and compatibility. Up to 340,000 usable gates in 0.25 µm. Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis, ... Original
datasheet

88 pages,
555.88 Kb

INTEL Core i5 760 k72 w5 PB7D pt35c PT35c transistor pt36c transistor pt36c datasheet abstract
datasheet frame
Abstract: ORCA® ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip. ... Original
datasheet

263 pages,
1111.91 Kb

ORLI10G OR4E06 transistor 30945 transistor l144c l146c pt36C L202C L235C L89C L41C l65c l31c L130C datasheet abstract
datasheet frame
Abstract: LatticeSCM XAUI to SPI4.2 July 2008 Reference Design RD1033 RD1033 Introduction The XAUI to SPI4.2 (X2S4) Bridge reference design is a cost-effective system solution for bridging SPI4.2 based network processors and 10G/10G 10G/10G+ Ethernet switching devices. On the XAUI side, the X2S4 optionally supports the HiGigTM protocol from Broadcom® and an over-clocked mode of operation supports the Broadcom HiGig+TM protocol with throughput rates of up to 12Gbps at the link layer. This solution leverages exi ... Original
datasheet

41 pages,
458.04 Kb

DS1005 014 UMI D3 L4 UMI PT36C HI higig pause frame 0x00900 marvell 618 datasheet pt36C transistor pt36c higig specification verilog code for spi4.2 to fifo higig2 EZchip "higig header" RD1033 10G/10G RD1033 abstract
datasheet frame
Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125G ... Original
datasheet

237 pages,
2548.5 Kb

W32 MARKING DS1004 PB124A PL84C PR55D pr94a diode SC115 SC15 SC25 transistor pt42c BA5 904 AF P SCM15 SC80 SC40 pr82a DS1004 abstract
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Shortform Datasheet Search Results

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PT36CB010 Kappa Networks Digitally Programmable Delay Line

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PT36CB020 Kappa Networks Digitally Programmable Delay Line

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PT36CB030 Kappa Networks Digitally Programmable Delay Line

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PT36CB050 Kappa Networks Digitally Programmable Delay Line

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PT36CB100 Kappa Networks Digitally Programmable Delay Line

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PT36CB150 Kappa Networks Digitally Programmable Delay Line

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PT36CB200 Kappa Networks Digitally Programmable Delay Line

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PT36CB400 Kappa Networks Digitally Programmable Delay Line

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PT36CB500 Kappa Networks Digitally Programmable Delay Line

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