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pt33a*

Catalog Datasheet Results Type PDF Document Tags
Abstract: LatticeECP/EC Family Data Sheet Version 02.2, March 2006 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features - - - - - - Extensive Density and Package Options · 1.5K to 32.8K LUT4s · 65 to 496 I/Os · Density migration supported sysDSPTM Block (LatticeECPTM Versions) · High performance multiply and accumulate · 4 to 8 blocks - 4 to 8 36x36 multipliers or ­ 16 to 32 18x18 multipliers or - 32 to 64 9x9 multipliers Embedded and Distribut ... Original
datasheet

159 pages,
862.15 Kb

DDR400 LFEC10 LFEC15 LFEC33 LFECP10 LFECP15 LFECP20 LFECP33 datasheet abstract
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Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 DS1004 Features ­ 1 to 7.8 Mbits memory ­ True Dual Port/Pseudo Dual Port/Single Port ­ Dedicated FIFO logic for all block RAM ­ 500MHz performance · Additional 240K to 1.8Mbits distributed RAM High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 Hi ... Original
datasheet

243 pages,
1343.14 Kb

umi u26 SCM15 SC80 SC40 SC25 SC15 SC115 426 b34 transistor pt42c transistor pt36c pt36C DS1004 DS1004 abstract
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Abstract: ORCA® ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC November 2003 Preliminary Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on ... Original
datasheet

242 pages,
1154.54 Kb

pt36C l200c transistor pt42c L200C equivalent datasheet abstract
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Abstract: Data Addendum March 2002 ORCA® OR3LxxxB Series Field-Programmable Gate Arrays Introduction Features High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply voltage for speed and compatibility. Up to 340,000 usable gates in 0.25 µm. Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis, ... Original
datasheet

88 pages,
555.88 Kb

INTEL Core i5 760 k72 w5 PB7D pt35c PT35c transistor pt36c transistor pt36c datasheet abstract
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Abstract: ORCA® ORSPI4 Dual SPI4 Interface and High-Speed SERDES FPSC May 2009 Data Sheet Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip. ... Original
datasheet

263 pages,
1111.91 Kb

ORLI10G OR4E06 transistor 30945 transistor l144c l146c pt36C L202C L235C L89C L41C l65c l31c L130C datasheet abstract
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Abstract: LatticeECP/EC Family Data Sheet Version 01.4, December 2004 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features - - - - - - Extensive Density and Package Options · 1.5K to 41K LUT4s · 65 to 576 I/Os · Density migration supported sysDSPTM Block (LatticeECPTM Versions) · High performance multiply and accumulate · 4 to 10 blocks - 4 to 10 36x36 multipliers or ­ 16 to 40 18x18 multipliers or - 32 to 80 9x9 multipliers Em ... Original
datasheet

158 pages,
601.62 Kb

LFECP33 LFEC10 LFEC15 LFEC33 LFECP10 LFECP15 LFECP20 DDR400 LFEC1E-3Tn100C datasheet abstract
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Abstract: LatticeSCM XAUI to SPI4.2 July 2008 Reference Design RD1033 RD1033 Introduction The XAUI to SPI4.2 (X2S4) Bridge reference design is a cost-effective system solution for bridging SPI4.2 based network processors and 10G/10G 10G/10G+ Ethernet switching devices. On the XAUI side, the X2S4 optionally supports the HiGigTM protocol from Broadcom® and an over-clocked mode of operation supports the Broadcom HiGig+TM protocol with throughput rates of up to 12Gbps at the link layer. This solution leverages exi ... Original
datasheet

41 pages,
458.04 Kb

DS1005 014 UMI D3 L4 UMI PT36C HI higig pause frame 0x00900 marvell 618 datasheet pt36C transistor pt36c higig specification verilog code for spi4.2 to fifo higig2 EZchip "higig header" RD1033 10G/10G RD1033 abstract
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Abstract: LatticeXP Family Data Sheet DS1001 DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 DS1001 Flexible I/O Buffer Features · Programmable sysIOTM buffer supports wide range of interfaces: - LVCMOS 3.3/2.5/1.8/1.5/1.2 - LVTTL ­ SSTL 18 Class I - SSTL 3/2 Class I, II ­ HSTL15 HSTL15 Class I, III - HSTL 18 Class I, II, III - PCI - LVDS, Bus-LVDS, LVPECL, RSDS Non-volatile, Infinitely Reconfigurable · Instant-on ­ powers up in microsec ... Original
datasheet

130 pages,
723.53 Kb

LFXP3C-3TN100I LFXP3C-4TN144C LFXP10 LFXP6C-3TN144I DDR333 LVCMOS33 LVCMOS25 LFXP10C-3F256I LFXP3C-4TN100C LFXP6 LFXP6C-3FN256I LFXP3C-3TN144C DS1001 DS1001 abstract
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Abstract: LatticeSC/M Family Data Sheet DS1004 DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 DS1004 Features High Performance FPGA Fabric · 15K to 115K four input Look-up Tables (LUT4s) · 139 to 942 I/Os · 700MHz global clock; 1GHz edge clocks 4 to 32 High Speed SERDES and flexiPCSTM (per Device) · Performance ranging from 600Mbps to 3.8Gbps · Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) · Low Tx jitter (0.25UI typical at 3.125G ... Original
datasheet

237 pages,
2548.5 Kb

W32 MARKING DS1004 PB124A PL84C PR55D pr94a diode SC115 SC15 SC25 transistor pt42c BA5 904 AF P SCM15 SC80 SC40 pr82a DS1004 abstract
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Abstract: LatticeECP2 Family Data Sheet Version 01.0, February 2006 LatticeECP2 Family Data Sheet Introduction February 2006 Advance Data Sheet Features · Source synchronous standards support ­ SPI4.2, SFI4, XGMII ­ High Speed ADC/DAC devices · Dedicated DDR and DDR2 memory support ­ DDR1 400 (200MHz) ­ DDR2 400 (200MHz) High Logic Density for System Integration · 6K to 68K LUTs · 192 to 628 I/Os sysDSPTM Block · 3 to 22 blocks for high performance multiply and accumulate ... Original
datasheet

104 pages,
1543.68 Kb

16X4 datasheet abstract
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