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5962-8515522SA Texas Instruments OT PLD, 10ns, CDFP20, CERAMIC, DFP-20 ri Buy
TIBPAL20R6-25CFN Texas Instruments OT PLD, 25ns, PQCC28, PLASTIC, CC-28 ri Buy
TIBPAL20R8-10CFN Texas Instruments OT PLD, 10ns, PQCC28, PLASTIC, CC-28 ri Buy

programmable slew rate control IO

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: CY8C24123A CY8C24123A CY8C24223A CY8C24223A CY8C24423A CY8C24423A PSoC® Programmable System-on-Chip PSoC® Programmable , (ADCs) • Up to 9-bit digital-to-analog converters (DACs) • Programmable gain amplifiers (PGAs) • Programmable filters and comparators ❐ Four digital PSoC blocks provide: • 8- to 32-bit timers and , 2 Port 1 Port 0 System Bus Global Digital Interconnect Precision, programmable clocking â , ❐ Electronically erasable programmable read only memory (EEPROM) emulation in flash Programmable ... Cypress Semiconductor
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datasheet

67 pages,
1219.69 Kb

CY8C24123A CY8C24223A CY8C24423A TEXT
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Abstract: Hysteresis and configurable pullup device on all input pins; Configurable slew rate and drive strength on all , Monitoring and Control · Wireless MBUS Standard (EN13757-4 EN13757-4:2005) This document contains information on a , , no Image Frequency response - Low current: Rx = 16mA, 100nA register retention - Programmable Pout , Central Processor Unit (CPU) with CPU clock rate up to: ­ 50.33 MHz at 3.6 V to 2.4V ­ 40 MHz at 2.4V to , (BDM) - System protection features ­ Programmable low voltage interrupt (LVI) ­ Optional watchdog ... Freescale Semiconductor
Original
datasheet

40 pages,
558.2 Kb

9S08 EN13757-4 EN137574 flash LGA60 LGA-60 adp9 marking code 9S08QE32 MC12311 ADP62 LGA60 EN-13757-4 TEXT
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Abstract: Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude , ] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function SLEWRATESEL DIF7 Adjust Slew Rate of DIF7 Bit 7 SLEWRATESEL DIF6 , Bit 7 REF Slew Rate Control RW Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 4 is Reserved REF Power , conditions, See Test Loads for Loading Conditions PARAMETER Slew rate Slew rate matching Voltage High Voltage ... Integrated Device Technology
Original
datasheet

16 pages,
210.55 Kb

xtal 3225 25 MHZ DT1X 9FGV0831 TEXT
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Abstract: €¢ board space Programmable Slew rate for each output; allows tuning for various line lengths , Rate Control Register Byte 2 Name Control Function SLEWRATESEL DIF7 Adjust Slew Rate of DIF7 Bit , Control/ REF Control Register Byte 3 Name Control Function Type RW Bit 7 REF Slew Rate Control RW , conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL Slew rate Trf Slew rate , Slew rate matching, Scope averaging on Trf Voltage High CONDITIONS 2 1 3 2 5 4 3 ... Integrated Device Technology
Original
datasheet

16 pages,
227.84 Kb

TEXT
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Abstract: . Reset clears the LINSL2:1 bits. Table 3. LIN Slew Rate Control and Device Low Power Mode , Âus Current Sense Operational Amplifier Output Slew Rate Phase Margin Open Loop Gain (17 , LIN Physical Layer: Bus Driver Timing Characteristics for Normal Slew Rate Propagation Delay TXD to , €” 10 — Âus LIN Physical Layer: Bus Driver Timing Characteristics for Slow Slew Rate (21 , Layer: Bus Driver Fast Slew Rate LIN High Slew Rate (Programming Mode) LIN Physical Layer, Transceiver ... Freescale Semiconductor
Original
datasheet

48 pages,
586.92 Kb

MC33689 TEXT
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Abstract: Product Term Clocks - Slew and Skew Programmable I/O (SASPI/OTM) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options - Six Global Output Enable Terms, Two Global OE Pins and One , macrocells and a fully populated, programmable AND-array with 160 logic product terms and 5 extra control , gate, a programmable register/latch/toggle flip-flop and the necessary clocks and control logic to , Delay D Q Slew Open rate drain 2.5V/3.3V Output To GRP PTSA PT Clock Shared PT Clock 0 Shared PT ... Lattice Semiconductor
Original
datasheet

25 pages,
272.63 Kb

5256VA TEXT
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Abstract: CY8C27143 CY8C27143, CY8C27243 CY8C27243 CY8C27443 CY8C27443, CY8C27543 CY8C27543 CY8C27643 CY8C27643 PSoC® Programmable System-on-ChipTM PSoC® Programmable System-on-Chip Features Powerful Harvard-architecture processor M8C processor speeds up , (DACs) · Programmable gain amplifiers (PGAs) · Programmable filters and comparators Eight digital PSoC , , programmable clocking Internal 2.5% 24- / 48-MHz main oscillator 24- / 48-MHz with optional 32 kHz crystal , programmable read only memory (EEPROM) emulation in flash Programmable pin configurations 25-mA sink, 10 ... Cypress Semiconductor
Original
datasheet

63 pages,
858.95 Kb

CY8C27143 CY8C27243 CY8C27443 CY8C27543 CY8C27643 TEXT
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Abstract: CY8C27143 CY8C27143, CY8C27243 CY8C27243 CY8C27443 CY8C27443, CY8C27543 CY8C27543, CY8C27643 CY8C27643 PSoC® Programmable System-on-Chip , Up to 9-Bit DACs · Programmable Gain Amplifiers · Programmable filters and comparators Eight , Analog Drivers PSoC CORE System Bus Global Digital Interconnect Precision, Programmable , protection modes EEPROM emulation in Flash Programmable Pin Configurations 25 mA Sink, 10 mA Source on , Functional Overview The PSoC family consists of many Programmable System-on-Chip Controller devices. These ... Cypress Semiconductor
Original
datasheet

53 pages,
695.09 Kb

CY8C27643 CY8C27543 CY8C27443-24PXI CY8C27443 CY8C27243 CY8C27143 TEXT
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Abstract: Quad-SPI reference clock frequency Notes: 1. 2. 3. 4. Test conditions: LVCMOS33 LVCMOS33, slow slew rate , -bit I/O mode. Test conditions: LVCMOS33 LVCMOS33, slow slew rate, 8 mA drive strength, 30 pF loads in 4 , Zynq-7000 All Programmable SoC (XC7Z010 XC7Z010 and XC7Z020 XC7Z020): DC and AC Switching Characteristics Product Specification DS187 DS187 (v1.6) April 24, 2013 Introduction The Zynq®-7000 All Programmable , I/O input voltage –0.55 VCCO_DDR + 0.55 V Programmable Logic (PL) VCCINT PL ... Xilinx
Original
datasheet

53 pages,
514.3 Kb

XC7Z010 XC7Z020 DS187 TEXT
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Abstract: Programmable Slew Rate Wide Supply Voltage Range Low Power CMOS 3-State Outputs TTL/CMOS Compatible Inputs , betw een the SRA (Slew Rate Adjust) pin and G N D . Resistor values betw een 2 k fl and 10 k£2 may be selected giving a slew rate which can be adjusted from 10 V/|is to 2.2 V/|is. This adjustm ent of the slew rate allows tailoring of the o u tp u t character­ istics to suit the interface cable being used , 6.0 7.0 Parameter 15 15 Us M s £Z H tzL O utput Slew Rate O utput Slew Rate O ... OCR Scan
datasheet

6 pages,
154.53 Kb

RS-232/RS-423 TEXT
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