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programmable slew rate control IO

Catalog Datasheet MFG & Type PDF Document Tags

1602D

Abstract: 9LRS 1 Description Reserved Reserved Slew Rate Control Reserved Slew Rate Control Reserved , Reserved Reserved Reserved Reserved Reserved Byte 6 Slew Rate Control Register Bit Pin 7 6 5 4 , 0.8V to 2.0V at default slew rate control setting. 2 All Long Term Accuracy and Clock Period , measured from 0.8V to 2.0V at default slew rate control setting. Output High Current IOH Notes 2, 4 , 2.0V at default slew rate control setting. Output High Current I OH MIN -50 ppm -15 15
Integrated Device Technology
Original

RS3187BL

Abstract: ICS9LRS RW 0 1 Default 1 1 1 1 1 1 1 1 Byte 6 Slew Rate Control Register Bit Pin 7 6 5 4 3 2 1 0 Name , Slew Rate Control Reserved Slew Rate Control Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 , measured from 0.8V to 2.0V at default slew rate control setting. All Long Term Accuracy and Clock Period , slew rate control setting. 2 3 4 Duty cycle, Peroid and Jitter are measured with respect to 1.5V , slew rate control setting. 2 3 4 4 4 All Long Term Accuracy and Clock Period specifications are
Integrated Device Technology
Original
Abstract: Slew Rate Control Reserved Slew Rate Control Reserved Reserved Reserved Type RW RW RW RW , Reserved Byte 6 Slew Rate Control Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved Reserved , measured from 0.8V to 2.0V at default slew rate control setting. Output High Current 2 IOH Notes , 2.0V at default slew rate control setting. Output High Current I OH MIN -50 ppm -15 15 , Pull-Up Resistor 32-pin MLF IDT® Programmable Timing Control Hub for Intel Based Systems Integrated Device Technology
Original

1602b

Abstract: tech 1602b Slew Rate Control Reserved Slew Rate Control Reserved Reserved Reserved Type RW RW RW RW , Reserved Byte 6 Slew Rate Control Register Bit Pin 7 6 5 4 3 2 1 0 Name Reserved Reserved , 0.8V to 2.0V at default slew rate control setting. 2 All Long Term Accuracy and Clock Period , measured from 0.8V to 2.0V at default slew rate control setting. Output High Current IOH Notes 2, 4 , 2.0V at default slew rate control setting. Output High Current I OH MIN -50 ppm -15 15
Integrated Device Technology
Original

ICS9LRS

Abstract: 9lrs RW 0 1 Default 1 1 1 1 1 1 1 1 Byte 6 Slew Rate Control Register Bit Pin 7 6 5 4 3 2 1 0 Name , Slew Rate Control Reserved Slew Rate Control Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 , measured from 0.8V to 2.0V at default slew rate control setting. All Long Term Accuracy and Clock Period , slew rate control setting. 2 3 4 Duty cycle, Peroid and Jitter are measured with respect to 1.5V , slew rate control setting. 2 3 4 4 4 All Long Term Accuracy and Clock Period specifications are
Integrated Device Technology
Original

9LRS

Abstract: ck505 1 Description Reserved Reserved Slew Rate Control Reserved Slew Rate Control Reserved , Reserved Reserved Reserved Reserved Reserved Byte 6 Slew Rate Control Register Bit Pin 7 6 5 4 , 0.8V to 2.0V at default slew rate control setting. 2 All Long Term Accuracy and Clock Period , measured from 0.8V to 2.0V at default slew rate control setting. Output High Current IOH Notes 2, 4 , 2.0V at default slew rate control setting. Output High Current I OH MIN -50 ppm -15 15
Integrated Device Technology
Original
Abstract: design â'¢ Output programmable slew rate controls Output Features: â'¢ 2 - pairs 0.7V differential , Low Current IOL VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Rising Edge Slew Rate tSLR Measured from 2.0 to 0.8 V Falling Edge Slew Rate tFLR Measured from 0.8 to 2.0 V Rise Time tr1 Measured , Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Average Maximum Output Voltage , Slew rate emastured through V_swing voltage range centered about differential zero 5 Vcross is Integrated Device Technology
Original

em 495 b12

Abstract: architecture including program m able slew -rate control O pen-drain output option Program m able m acrocell , / O pin to m acrocell registers Program m able output slew -rate control Program m able ground pins , . The slew rate control affects both the rising and falling edges of the output signal. 614 Altera , delay. M AX 7000A devices also provide an option that reduces the slew rate of the output buffers, m , Device Family Data Sheet Programmable Speed/Power Control M AX 7000A devices offer a pow er-saving
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12v AC to DC CIRCUIT DIAGRAM

Abstract: impedence time from CK/ CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL , DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 , the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4
Samsung Electronics
Original
Abstract: slew rate control affects both the rising and falling edges of the output signal. Design Security , buffer and pad delay slow slew rate = off V c c io = 2.5 V toD3 O utput buffer and pad delay , off V c c io = 3-3 V tzX2 O utput buffer enable delay slow slew rate = off V c c io = 2.5 V , to D 2 O utput buffer and pad delay slow slew rate = off V c c io = 2.5 V to D 3 O utput , delay slow slew rate = off V c c io = 3-3 V tzX2 O utput buffer enable delay slow slew rate = -
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EPC1441

Abstract: EPF6010A output buffer enable delay, slow slew rate = on C1 = 35 pF (4) tIOE Output enable control delay , Slew-Rate Control Altera Corporation 23 FLEX 6000 Programmable Logic Device Family Data Sheet , buffer and pad delay, slow slew rate = off, VCCIO = VCCINT C1 = 35 pF (2) tOD2 Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage C1 = 35 pF (3) tOD3 Output buffer and pad delay, slow slew rate = on C1 = 35 pF (4) tXZ Output buffer disable delay C1 = 5 pF
Altera
Original

LMP8100AMA

Abstract: AMA TOP MARKING 0.1 pA Input noise voltage 12 nV/ Hz Unity gain bandwidth 33 MHz Slew rate 12 V/·s , Rail-to-Rail output swing 2.7 Volt Supply Max 5 Volt SPI-Microwire Slew Rate 12 Volts/usec V , /s Slew rate 20 mA Output current 2.7V to 5.5V Supply voltage range 5.3 mA Supply current , / µVPP 16 V/V BW Bandwidth SR Slew Rate (Note 7) PSRR Power Supply Rejection , = 0, Gain = 2 V/V % 9.5 SR Slew Rate (Note 7) PSRR Power Supply Rejection Ratio
National Semiconductor
Original
Abstract: ) 0.5 Input Slew Rate(for I/O pins) tSL(IO) 0.5 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 , (t JIT(crosstalk) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate , This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup Samsung Electronics
Original

DDR200

Abstract: DDR266 +0.8 tSL(I) 0.5 Input Slew Rate(for I/O pins) tSL(IO) 0.5 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 Output Slew Rate Matching Ratio(rise , +0.75 -0.8 +0.8 tSL(I) 0.5 Input Slew Rate(for I/O pins) tSL(IO) 0.5 Output Slew , from CK/CK DQS-in hold time Input Slew Rate(for input only pins) 0.35 1.1 0.9 0.35 1.1 , Slew Rate Derating Input Setup/Hold Slew Rate tIS tIH (V/ns) (ps) (ps) 0.5 0 0
Samsung Electronics
Original

CA3080

Abstract: programmable slew rate control IO LiC Variable Operational Amplifiers CA3094 Programmable Power Switch/Amplifier CA3080 Programmable Op-Amp â'¢Input control permits user to vary voltage, power bandwidth, slew rate, input and output , gain control â'¢Slew rate (unity gain, compensated): 50 V//*s â'¢Flexible supply voltage range:  , frequency response and slew rate without sacrificing power. CA3060: 3 variable op-amps on one chip plus a , '¢ Programmable: strobing, gating, squelching, age capabilities â'¢Capable of delivering 3 W average or 10
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CA3Q94 CA3078 CA3078A programmable slew rate control IO ca3080 amp
Abstract: slew rate = off, v ccio = 5.0 v Output buffer and pad delay, Slow slew rate = off, V c c io = 3-3 V , devices also provide an option that reduces the slew rate of the output buffers, minimizing noise , IOC has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces board-level noise and adds a nominal timing delay to the output buffer delay (tO D ) parameter. The fast slew rate should be used for speed-critical outputs in system s that -
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280-P 304-P

PJO 399

Abstract: PJO 389 specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling , buffer and pad delay slow slew rate = off V cc io = 3-3 V C1 = 0.3 0.3 2.4 2.8 0.5 2.5 2.5 0.2 35 pF , ) compatible Bus friendly architecture including programmable slew-rate control Open-drain output option , path from I/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins , option that reduces the slew rate of the output buffers, minimizing noise transients when
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PJO 399 PJO 389 pjo 489 PJO 499 B13128 7512A MAX7000AE EPM7128A EPM7256A 7000S 7000B EPM7032AE
Abstract: architecture including pro g ram m ab le slew -rate control O pen-d rain o u tp u t o p tion P rogram m able , able o u tp u t slew -rate control Softw are design su p p o rt an d autom atic place-and-route p ro v , slew rate = off N ote (1) V c c io = 3-3 V toD2 O utput buffer and pad delay C1 = 3 5 pF, slow slew rate = off N ote (6) V c c io = 2-5 V toD3 O utput buffer and pad delay C1 = 35 pF slow slew rate = on V c c io = 3 -3 V or 2.5 V tz x i O utput buffer enable delay slow slew -
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7000AE

EPM7064 100-Pin Package Pin-Out Diagram

Abstract: epm 7032 slc 44 enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. In , Control The output buffer for each MAX 7000E and MAX 7000S I/O pin has an adjustable output slew rate , 4 ns lZX2 Output buffer enable delay Slow slew rate = off V c c io = 3 -3 V C1 = 35 pF Note (7) 4.5 4.5 ns lZX3 Output buffer enable delay Slow slew rate = on V c c io = 5 0 v , lZX2 Output buffer enable delay Slow slew rate = off V c c io = 3 -3 V C1 = 35 pF, Note (7
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EPM7064 100-Pin Package Pin-Out Diagram epm 7032 slc 44 EPM7032 EPM7032V EPM7032S EPM7064 EPM7064S EPM7096

AXP 188 IC

Abstract: AXP 192 each IO E has an adjustable output slew rate that can be configured for low-noise or high-speed perform ance. A slow er slew rate reduces system noise and adds a m axim um d elay of 4 ns. The fast slew rate , control is availab le for the inputs to both L E s and IO Es. Therefore, if a register is cleared b y o n , 8000 Programmable Logic Device Family Each L A B provides four control signals that can be used in a , esigners can specify the slew rate on a pin-by-pin basis du ring design en try or assign a d efault slew
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AXP 188 IC AXP 192 EPF8282V EPF8636A
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