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SN74LS00DRG4 Texas Instruments Quad 2-input positive-NAND gates 14-SOIC 0 to 70 ri Buy
SN74LS00DR Texas Instruments Quad 2-input positive-NAND gates 14-SOIC 0 to 70 ri Buy
SN74LS00DE4 Texas Instruments Quad 2-input positive-NAND gates 14-SOIC 0 to 70 ri Buy

pin diagram of ic 74ls00

Catalog Datasheet Results Type PDF Document Tags
Abstract: CAPABILITY 10 LSTTLLOADS BALANCED PROPAGATION DELAYS tPLH = tpHL B1R (Plastic Package) F1R (Ceram ic Package) PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE I Io h I = Io l = 4 , pd (*) pF (*) Cpd is defined as the value of the IC's internal equivalent capacitance which is , same high speed per formance of LSTTL combined with true CM OS low power consumption. The internal circuit is compo sed of 3 stages including buffer output, which ena bles high noise immunity and stable ... OCR Scan
datasheet

4 pages,
98.64 Kb

pin diagram of 74ls00 74LS00 circuit diagram with voltage of ic 74ls00 74LS00 gate diagram 74ls00 circuit diagram IC TTL 74LS00 74LS00 integrated circuit pin diagram of ic 74ls00 datasheet abstract
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Abstract: PIN CONFIGURATION (Top view) complete time of day clock alarm, a hundred year calendar, also a 26 x , microcomputer. This pin provides easy zero setting for the ''seconds" independently of the CPU- When A D J - il , ith ty p ic a l pins D nPi Dì Dì are connected to the corresponding pins of the Z 8 (1 T h e C 5" pin of the RP5C01 RP5C01 should connect with the IO R Q pin, or one A. A, A, Al RDWRCS " Z 80 , one B it of the 8085 Connection Diagram Address Bus (e.g.pin A 0). When the crystal oscillator used ... OCR Scan
datasheet

14 pages,
249.33 Kb

74LS74 timing diagram IC - 74LS04 IC PIN CONFIGURATION OF 74LS04 IC 74LS74 74LS04 pin DIAGRAM OF IC 74ls04 74ls74 pin configuration RP5C01 pin diagram of ic 74ls00 pin DIAGRAM OF IC 74ls74 IC 8085 pin diagram RP5C01 abstract
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Abstract: not released in the range of 30 to 59 secs by countup until the full minute expires. A D D R ESS pin , Circuit Nil 74LS74 74LS74 (N O T E 1) 74LS00, 74LS04 74LS04 a w ith ty p ic a l RP5C 01 c o c o r r e s p o n d in g , the Address Bus (e.g.A0). T h e C S pin of the C P U (Z80,8085,6800) are presented hereunder. X , 8085 {the sam e sy m b o ls a re used). T h e C S pin o f the RP5C01 RP5C01 should connect with one B it of , , Address Bus of the symbols are the same). T h e R D , W R , p ins of th e Connection Diagram RP5C01 RP5C01 sh o u ... OCR Scan
datasheet

14 pages,
253.75 Kb

pin configuration and OF IC 74ls04 circuit CLOCK ALARM 8085 4LS74 pin diagram of 74ls74 pin diagram and block diagram of 74ls74 pin DIAGRAM OF IC 74ls74 8085 TEMPERATURE CONTROLLER 8085 timing diagram CLOCK ALARM 8085 pin DIAGRAM OF IC 74ls04 SK 8085 equivalent RP5C01 RP5C01 RP5C01 abstract
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Abstract: H H H L L H H H PIN CONFIGURATION (TOP VIEW) Outline 14P4 14P2P 14P2P LOGIC DIAGRAM (EACH GATE , 19 i 16 -4- 113 23 _ 19_ 113 23 _19_ 10 Note 2 : CpD is the internal capacitance of the IC , The M74HC00 M74HC00 ts a semiconductor integrated circuit consisting of four 2-input positive-logic NAND , dissipation: 5,uW/package (max) (VCc=5V, Ta=25'C, quiescent state) • High noise margin: 30% of Vcc, min (VCC=4.5V, 6V) • Capable of driving 10 LSTTL loads • Wide operating voltage range: VCc=2~6V • Wide ... OCR Scan
datasheet

3 pages,
85.12 Kb

4000B 74LS00 74LS00 CMOS CI 74LS00 M74HC00DP m74hcoodp of ic 74ls00 74ls00 series 74LS00 function table IC PIN CONFIGURATION OF 74LS00 M74HCOO 74ls00 circuit diagram 74LS00 pin configuration pin diagram of 74ls00 74HC00P 74HC00DP 74HC00P abstract
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Abstract: and fluorescent lamps and is selectable at Pin 7 for low or high data rates. The LT1328 LT1328's ease of use , V V V V V V V V CONDITIONS Current Out of Pin 1 (SIR), Pulse Width 1.6p.s, Period 8.7|xs Current Out of Pin 1 (FIR, 4ppm), Pulse Width 125ns, Period 500ns Current Out of Pin 1 DC to 120Hz, Current Out of Pin 1 No Input Signal Minimum Input Current Pulse IpD Maximum Input Current Maximum , Current vs Frequency V S = 5V1 CBIAS = 1OOOpF CURRE NT IS SOURC ED OUT OF: PIN 1 o 1 0 0 CF|LT= 3 ... OCR Scan
datasheet

12 pages,
369.56 Kb

pin diagram of ic 74ls00 LT1328 LT1328 abstract
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Abstract: DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL , Capacitance Unit (*) CPD is defined as the value of the IC's internal equivalent capacitance which is , fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages including buffer output , M74HCT00C1R M74HCT00C1R PIN CONNECTIONS (top view) This integrated circuit has input and output characteristics that ... Original
datasheet

9 pages,
230 Kb

74ls00 circuit diagram 74LS00 circuit diagram with voltage IC TTL 74LS00 M54HCT00 M54HCT00F1R M74HCT00 M74HCT00B1R M74HCT00C1R M74HCT00M1R IC 74LS00 M74HCT00B1 74LS00 gate diagram pin diagram of ic 74ls00 M54HCT00 abstract
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Abstract: DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL , Capacitance Unit (*) CPD is defined as the value of the IC's internal equivalent capacitance which is , fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages including buffer output , M74HCT00C1R M74HCT00C1R PIN CONNECTIONS (top view) This integrated circuit has input and output characteristics that ... Original
datasheet

9 pages,
266.63 Kb

TTL 74ls00 74LS00 TTL M54HCT00 M54HCT00F1R M74HCT00 M74HCT00B1R M74HCT00C1R M74HCT00M1R 74LS00 circuit diagram with voltage 74LS00 CMOS 74LS00 gate diagram pin diagram of ic 74ls00 54/74LS00 M54HCT00 abstract
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Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , 4 D/A Latch DESCRIPTION OF PIN FUNCTIONS DAC707 DAC707 DESIGNATOR VOUT VDD DESCRIPTION Voltage , amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit. , output op amp for the DAC708 DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 DAC708. , the DAC708 DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 DAC708. Bipolar offset. ... Original
datasheet

13 pages,
134.25 Kb

pin diagram of ic 74ls00 DAC707 DAC708 DAC709 16-BIT DAC707 abstract
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Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , , 0.0022µF to 0.01µF. ® DAC707/708/709 DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN FUNCTIONS DAC707 DAC707 , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , Refer to Connection Diagram for connection of external op amp to DAC708 DAC708. D13 Data bit 13 15 ... Original
datasheet

13 pages,
134.27 Kb

pin diagram of 74ls00 DAC709 DAC708 709b DAC707 pin diagram of ic 74ls00 16-BIT DAC707 abstract
datasheet frame
Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , 4 D/A Latch DESCRIPTION OF PIN FUNCTIONS DAC707 DAC707 DESIGNATOR VOUT VDD DESCRIPTION Voltage , amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit. , output op amp for the DAC708 DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 DAC708. , the DAC708 DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 DAC708. Bipolar offset. ... Original
datasheet

13 pages,
135.97 Kb

uv 709 pin diagram of 74ls00 DAC707 DAC708 DAC709 16-BIT DAC707 abstract
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Kaleidoscope 30/06/2005 641.53 Kb ZIP doc_eeschema.zip
graphic elements 10.5.3 - Graphic elements of text type 10.6 - Pin creation and editing 10.6.1 - Pins schematic diagram design). The use of aliases is a very interesting method of creating complete but compact editor), the reference (U, IC, R...), the number of parts per package (for example a standard component parts will be published or created together. If you increase the number of parts after pin creation visibility of the pin number and pin name text (these texts will be visible if the corresponding options are
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Kaleidoscope 20/05/2005 149.4 Kb SXW eeschema_chapter10_en.sxw
. PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 . SYMMETRICAL OUTPUT IMPEDANCE z I OH z = I the value of the IC's internal equivalent capacitance which is calculated from the operating current ) PIN CONNECTIONS (top view) NC = No Internal Connection INPUT AND OUTPUT EQUIVALENT CIRCUIT . silicon gate C 2 MOS technology. It has the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The internal circuit is com- posed of 3 stages including buffer
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2097-v3.htm
STMicroelectronics 25/05/2000 9.29 Kb HTM 2097-v3.htm
reduction of power consumption. DESCRIPTION 1/9 TRUTH TABLE A B Y L L H L H H H L H H H L PIN (*) Power Dissipation Capacitance 40 pF (*) C PD is defined as the value of the IC's internal Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection INPUT AND OUTPUT EQUIVALENT CIRCUIT DRIVE CAPABILITY 10 LSTTL LOADS . BALANCED PROPAGATION DELAYS t PLH = t PHL . PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 . SYMMETRICAL OUTPUT IMPEDANCE z I OH z = I OL = 4 mA (MIN.) The M54
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2097.htm
STMicroelectronics 20/10/2000 9.8 Kb HTM 2097.htm
(Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal ) . OUTPUTS DRIVE CAPABILITY 10 LSTTL LOADS . BALANCED PROPAGATION DELAYS t PLH = t PHL . PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 . SYMMETRICAL OUTPUT IMPEDANCE z I OH z = I OL = 4 mA (MIN.) The M54 the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The internal circuit is com- posed of 3 stages including buffer output, which en- ables high noise immunity and stable
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/2097-v1.htm
STMicroelectronics 02/04/1999 7.53 Kb HTM 2097-v1.htm
(Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal ) . OUTPUTS DRIVE CAPABILITY 10 LSTTL LOADS . BALANCED PROPAGATION DELAYS t PLH = t PHL . PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 . SYMMETRICAL OUTPUT IMPEDANCE z I OH z = I OL = 4 mA (MIN.) The M54 the same high speed per- formance of LSTTL combined with true CMOS low power consumption. The internal circuit is com- posed of 3 stages including buffer output, which en- ables high noise immunity and stable
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STMicroelectronics 14/06/1999 7.49 Kb HTM 2097-v2.htm