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SN74LS00DRG4 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14 visit Texas Instruments
SN74LS00N-10 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14 visit Texas Instruments
SN74LS00FN Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PQCC20 visit Texas Instruments
SN74LS00N3 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14 visit Texas Instruments
SN74LS00DBR Texas Instruments Quad 2-input positive-NAND gates 14-SSOP 0 to 70 visit Texas Instruments
SN74LS00NE4 Texas Instruments Quad 2-input positive-NAND gates 14-PDIP 0 to 70 visit Texas Instruments

pin diagram of ic 74ls00

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Abstract: A B L L H L H H H L L H H H PIN CONFIGURATION (TOP VIEW) Outline 14P4 14P2P LOGIC DIAGRAM , capacitance of the IC calculated from operation supply current under no-load conditions, (per gate) The power , DESCRIPTION The M74HC00 ts a semiconductor integrated circuit consisting of four 2-input positive-logic NAND , dissipation: 5,uW/package (max) (VCc=5V, Ta=25'C, quiescent state) â'¢ High noise margin: 30% of Vcc, min (VCC=4.5V, 6V) â'¢ Capable of driving 10 LSTTL loads â'¢ Wide operating voltage range: VCc=2~6V â -
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M74HC00P 74LS00 transfer function 74LS00 gate diagram pin diagram of 74ls00 74LS00 pin configuration 74ls00 circuit diagram M74HC00DP 4000B 74LS00
Abstract: 10 LSTTLLOADS BALANCED PROPAGATION DELAYS tPLH = tpHL B1R (Plastic Package) F1R (Ceram ic Package) PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE I Io h I = Io l = 4 , C pd (*) pF (*) Cpd is defined as the value of the IC's internal equivalent capacitance which , same high speed per formance of LSTTL combined with true CM OS low power consumption. The internal circuit is compo sed of 3 stages including buffer output, which ena bles high noise immunity and stable -
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74LS00 integrated circuit IC TTL 74LS00 of ic 74ls00 74LS00 circuit diagram with voltage 74ls00 tr tf 74HCT00 54/74LS00 M54/74HCT00 M54/74HC T00F1 T00B1R M54/M
Abstract: DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL , Capacitance Unit (*) CPD is defined as the value of the IC's internal equivalent capacitance which is , fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages including buffer output , M74HCT00C1R PIN CONNECTIONS (top view) This integrated circuit has input and output characteristics that STMicroelectronics
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M54HCT00 M74HCT00 M54HCT00F1R M74HCT00M1R M74HCT00B1R 74LS00 CMOS M74HCT00B1 M54/M74HCT00
Abstract: DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS00 SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL , Capacitance Unit (*) CPD is defined as the value of the IC's internal equivalent capacitance which is , fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages including buffer output , M74HCT00C1R PIN CONNECTIONS (top view) This integrated circuit has input and output characteristics that STMicroelectronics
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IC 74LS00 P027A
Abstract: to inputs of GATE 3 Qc 6 Qa Qc 7 Q b Qc 9 1/6 74LS04 or1/4 74LS00 or1 , '¢ â'¢ â'¢ Pin Configuration Internal Look-Ahead for Fast Counting Carry Output for n-Bit , coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of , ) edge of the clock input wave form. f1' CLEAR CLOCK â'ž A Q Qc LOAD B C 3 B , Dual In Line Package Ceram ic Dual In Line Package This counter is fully programmable; that is the -
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74ls163 function table GD54/74LS163A 4DE6757 000424G
Abstract: . (74HC) â'¢ High noise immunity characteristic of CMOS â'¢ Diode protection on all inputs Logic Symbol and Logic Diagram 00 Suffix-Blank : Plastic Dual In Line Package Suffix-J : Ceram ic Dual , identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are , . Pin Configuration u 1 [T A m vcc [T 73] 4B 1Y [T Tj~| 4A 2A [T , Features â'¢ Low Power consumption characteristic of CMOS devices â'¢ Output drive capability: 10 LS TTL -
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GD54/74HC00 GD54/74HCT00
Abstract: (Plastic Package) F1R (Ceram ic Package) PIN AN D FU NC TIO N C O M PATIB LE W ITH 54/74LS00 S Y M M ETR IC AL O U T P U T IM PEDANCE | Io h | = I o l = 4 m A (MIN.) D ES CR I PT ION The M 54/74HCT00 , . It has the same high speed per form ance of LSTTL combined w ith true C M O S low pow er consumption. The internal circuit is com posed of 3 stages including buffer output, which en ables high noise , a reduction of pow er consumption. I NPUT AND O U T P U T E Q U I V A L E N T C I RC UI T M 1R -
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74LS00 gate diagram nand 54/74HC 54HCT00F
Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , 4 D/A Latch DESCRIPTION OF PIN FUNCTIONS DAC707 DESIGNATOR VOUT VDD DESCRIPTION Voltage , amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit , output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 , the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. Bipolar offset Burr-Brown
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uv 709 DAC709 16-BIT DAC707JP/KP DAC708/709
Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , 4 D/A Latch DESCRIPTION OF PIN FUNCTIONS DAC707 DESIGNATOR VOUT VDD DESCRIPTION Voltage , amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit , output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 , the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. Bipolar offset Burr-Brown
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74HTC specification of 74ls00
Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , ) Bypass, 0.0022uF to 0.01uF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 Burr-Brown
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TTL 74ls00 analog devices ic 74LS00 lead side brazed hermetic op amp 709 datasheet of ic 74ls00 IC data sheet 74LS00
Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , ) Bypass, 0.0022uF to 0.01uF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 Burr-Brown
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709b 7407 connection diagram
Abstract: ) Bypass, 0.0022ÂuF to 0.01ÂuF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , latch. GA Gain adjust pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13 , output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 , DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D11 Data bit 11 , (The DAC708 and DAC709 are in 24-pin packages) ® 5 DAC707/708/709 DISCUSSION OF Burr-Brown
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Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , ) Bypass, 0.0022uF to 0.01uF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 Burr-Brown
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Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , 4 D/A Latch DESCRIPTION OF PIN FUNCTIONS DAC707 DESIGNATOR VOUT VDD DESCRIPTION Voltage , amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit , output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708 , the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. Bipolar offset Burr-Brown
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Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , ) Bypass, 0.0022uF to 0.01uF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 Burr-Brown
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74LS00 TTL 74ls00 series 74LS00 TTL datasheet texas 74 series TTL logic gates 74 HTC 08 7407 ic configuration
Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , ) Bypass, 0.0022uF to 0.01uF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 Burr-Brown
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DAC707KP MODEL 708 equivalent 74LS161A TIL117
Abstract: ) Bypass, 0.0022ÂuF to 0.01ÂuF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14) Input for data bit , DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 , Connection Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO , DAC709 are in 24-pin packages) ® 5 DAC707/708/709 DISCUSSION OF SPECIFICATIONS the MSB Burr-Brown
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Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , ) Bypass, 0.0022uF to 0.01uF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 Burr-Brown
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DAC709KH
Abstract: 125°C TJ and the case temperature (as measured at pin 1 or the back of the display) should not exceed , diagram, and represents the single wavelength which defines the color of the device. 8. The luminous , pin. Figure 5 is the block diagram for the displays. High true data in the shift register enables , intensity control and reduction in power consumption. COLUMN DRIVE INPUTS Figure 5. Block Diagram of , resistance from IC junction to ambient of 60°C/watt/device is possible up to ambient temperature of 37 Agilent Technologies
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HDSP2450 ic 7490 which divide by 2 HDSP-2010 HDSP-2000 CI 74LS00 74151 Multiplexer HDSP-2301 HDSP-2302 HDSP-2303 HDSP-2301/2303 HDSP-2301/-2302/-2303 HNCP37
Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , ) Bypass, 0.0022uF to 0.01uF. ® DAC707/708/709 4 Digital Inputs DESCRIPTION OF PIN , connected to the summing junction of the output amplifier. Refer to Block Diagram. 5 D6 (D14 , pin. Refer to Connection Diagram for gain adjust circuit. 6 D5 (D13) Data bit 5 (LB) or data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 Burr-Brown
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74LS00 clock frequency 74LS00 DATA 74LS00 impedance
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