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Part Manufacturer Description Datasheet BUY
SN74147N Texas Instruments 10-Line to 4-Line BCD Priority Encoder 16-PDIP 0 to 70 visit Texas Instruments
CD4504BKMSR Intersil Corporation HEX TTL/CMOS TO CMOS TRANSLATOR, INVERTED OUTPUT, CDFP16 visit Intersil
TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments
SN74122J-00 Texas Instruments TTL/H/L SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14 visit Texas Instruments
SN74123J Texas Instruments TTL/H/L SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP14 visit Texas Instruments
SN74122N-10 Texas Instruments TTL/H/L SERIES, MONOSTABLE MULTIVIBRATOR, PDIP14 visit Texas Instruments

pin diagram of 74147 TTL IC

Catalog Datasheet MFG & Type PDF Document Tags

IC 74147

Abstract: encoder IC 74147 Signetics Logic Products Product Specification Encoder 74147 LOGIC DIAGRAM LD0Î950S , .) 74147 PARAMETER ic a i b U N U iiiu n » Min VoH VOL VlK ! 1 hH IlL UNIT Typ2 3.3 0.2 0.4 -1.5 1.0 40 , Signetics 74147 Encoder 10-Une-To-4-Line Priority Encoder Product Specification Logic , Used in code converters and generators TYPE 74147 TYPICAL PROPAGATION DELAY 10ns TYPICAL SUPPLY , -line-to-4-line priority encoding function by use of the implied decimal "zero." The "zero" is encoded when all nine data
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encoder IC 74147

Abstract: IC 74147 circuit diagram output can drive one TTL low-power Schottky load. The CD40147B Is functionally similar to the TTL 54/74147 if pin 15 is tied low. The CD40147B types are supplied in 16-lead ceramic dual-in-line packages (D , encoding of the inputs to ensure that only the highest-order data line Is encoded. Ten data input lines , all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' ' Series CMOS Devices" â  Maximum input current of 1 /iA at 18 V over full package-temperature
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CD40147BH encoder IC 74147 IC 74147 circuit diagram pin diagram of 74147 TTL IC IC 74147 74147 ic pin diagram priority encoder 74147 0Q37733
Abstract: CD40147BMS is func­ tionally similar to the TTL 54/74147 if pin 15 is tied low. The CD40147BMS packages , , 5, 10, 12, 15 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E , 8 ^ 12] 2 â'¢ Maximum Input Current of 1 j iA at 18V Over Full Pack­ l age Temperature , '¢ Standardized Sym metrical Output Characteristics â'¢ Meets All Requirements of JEDEC Tentative Standard No -
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CD40147BM
Abstract: Characteristics â'¢ Meets All Requirements of JEDEC Tentative Standard No. 13B, â'Standard Specifications for Description of 'B' Series CMOS Devicesâ' Functional Diagram Applications Keyboard Encoding â'¢ â , drive one TTL low power Schottky load. The CD40147BMS is func­ tionally similar to the TTL 54/74147 , pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except , Input Current of 1|iA at 18V Over Full Pack­ age Temperature Range; 100nA at 18V and +25°C »H cQ -
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VDD-10V

pin diagram of 74147

Abstract: pin diagram encoder 74147 TTL low power Schottky load. The CD40147BMS is functionally similar to the TTL 54/74147 if pin 15 is , Characteristics · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" Functional Diagram Applications · Keyboard Encoding · 10 Line , VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND , 2 C 6 11 1 B 7 10 9 VSS 8 9 A · Maximum Input Current of 1µA at 18V Over Full
Harris Semiconductor
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pin diagram of 74147 pin diagram encoder 74147 74147 pin diagram and truth table 74147 Applications of priority encoder 74147 74147 pin diagram and function table

IC 74147

Abstract: 74147 pin diagram and truth table CD40147BMS is functionally similar to the TTL 54/74147 if pin 15 is tied low. The CD40147BMS is supplied in , VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND , VSS 8 9 A · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at , of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" Functional Diagram Applications · Keyboard Encoding · 10 Line to BCD Encoding 9 ·
Intersil
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datasheet IC 74147 data sheet IC 74147 IOH15 ic datasheet 74147 semiconductor 74147 IC 74147 ACTIVE LOW

encoder IC 74147

Abstract: IC 74147 40147BM S is func tionally similar to the T TL 54/74147 if pin 15 is tied low. The C D 40147BM S is , resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± , Current at 20V · 5V, 10V and 15V Parametric Ratings · Maximum Input Current of 1|iA at 18V Over Full Pack , Characteristics · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" Pinout CD40147BMS TOP VIEW U Ü ] VDD lo 4E «Q ·G cG b jÜ o
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40147B I-90S

IC 74147

Abstract: encoder IC 74147 CD40147BMS is functionally similar to the TTL 54/74147 if pin 15 is tied low. The CD40147BMS is supplied in , VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND , VSS 8 9 A · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at , of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" Functional Diagram Applications · Keyboard Encoding · 10 Line to BCD Encoding 9 ·
Intersil
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74147 logic diagram

74LS14 GS

Abstract: 74LS14 DATA logic diagram 3 TTL DEVICES 3556 Texas ^ In s tru m e n ts Pin n u m bers sho w n on , include testing of all param eters. Te x a s * In s t r u m e n t s POST O F F IC E BOX 225012 · D A L , r u m e n t s POST O F F IC E B O X 225012 · D A L L A S . T E X A S 75265 3.557 TTL DEVICES , m e n t s POST O F F IC E BOX 225012 · D A L L A S , T E X A S 75265 3-559 TTL DEVICES PA , 54LS14 8 . . . J OR W PACKAGE S N 74147, S N 7414 8 . . . J OR N PACKAGE S N 74LS14 7, SN 74LS 14 8 . . .
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74LS14 GS 74LS14 DATA IC 74LS14 SN54147 SN54148 SN54LS147 SN54LS148 SN74J47 SN74148

truth table for ic 74138

Abstract: 16CUDSLR truth table C om plete sym bol library of basic gates and over 120 TTL m acro functions S u p p o rt for , cycles Elim ination of un u sed gates A utom atic pin and p art assignm ents SALSA logic m inim ization , Easy definition of in p u ts w ith state tables, vector patterns, or predefined patterns State table or , desig n er to choose the m ethods that best suit each design. Figure 1 show s a block d iagram of A+PLUS. A+PLUS includes the A ltera Design Processor (ADP), w hich consists of integ rated m od u les that
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truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu pin diagram of IC 74184

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 '" Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS , -42-41 Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL CMOS ,   t-42-41 Type No. Function block name Logic function Max. No. of fan-outs Interface level TTL , function Max. No. of fan-outs Interface level TTL CMOS High current I/O with pull down (16mA) B , in the Comments column, the addition of a terminal for each bit of an internal flip-flop makes the IC
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IC 3-8 decoder 74138 pin diagram binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder MSM91H000 72MS40

MT3329

Abstract: gps mtk ii module 2010-11-29 Description First Release (Draft) Update System Block and Pin Definition of Pin 7 First , .10 2.5 Description of I/O Pin , Pin 1 PCB Bottom View This document is the exclusive property of GlobalTop Tech Inc. and should , Rev. A08 2.5 Description of I/O Pin VCC (Pin1) The main DC power supply of the module, the , chipset that has automatic antenna switching support This document is the exclusive property of
GlobalTop Technology
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GR9903-DS000E MT3329 gps mtk ii module Mediatek Gps Mt3329 mediatek MT3329 gps MTK command MTK MT3329

Mediatek Gps Mt3329

Abstract: MT3329 .11 2.5 Description of I/O Pin , Sheet 2.5 Description of I/O Pin VCC, Pin1 The main DC power supply for the module. The voltage , of RTCM protocol (TTL level), if not used keep floating' RTCM is not enabled by default, please , superefficient low power consumption. This document is the exclusive property of GlobalTop Tech Inc. and should not be distributed, reproduced, into any other format without prior permission of GlobalTop Tech
GlobalTop Technology
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gps tracker circuit diagram Mediatek MT3329 chip mediatek mtk RTCM GPS patch antenna magnetic mount mediatek platform design GR9903-DS000D

LEAPER-3

Abstract: 74189 environment of development. Additional, the Company has been qualified by major IC manufacturer such as ATMEL , the"Cartridge modules" you can have all sorts of special IC programming systems. The SU-2000 offers two modes , matrix LCD display *Test Socket:One position for 28-pin IC socket *Operating Key: (1) 6 Function keys , hook x 1 40-pin IC socket x 1 DC power supply x 1 EXT CRYSTAL adaptor x1 System software disk User , x1 *16-bit 40-pin module + flat cable x1 *4 signal line hook x1 *28-pin IC socket x2 *System
Leap Electronic
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LEAPER-3 74189 7489 sram 89C51 interfacing with lcd display 4N34 ic 74192 pin configuration PIC16C52/54/54A PIC16C55/56/57/57A/58A PIC12C508/509 PIC16C61 PIC16C620/621/622 PIC16C71/710

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC gate delays in the order of 0.4 ns · 200 MHz toggle frequency · ADVANCELL(TM > compatible · TTL/CMOS , for most requirements. Output drive may be increased from the basic 1mA to a maximum of 48mA per pin , trigger input cells offer 1.2V of hysterisis for CMOS levels and 0.7V for TTL levels. More details of , = change of input rise/fall times form the nominal value For example, if a TTL input buffer accepts , 0 M H z , has 2 2 in p u ts a n d 4 0 o u tp u ts of w h ic h 10 are of 4 m A d riv e s tre n g th a
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74LS82 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 la 4508 ic schematic diagram advantages for ic 7473 TC140G SC12D4 SC18D4 SC27D4 SC37D4 SC44D4

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 CELL An unprogrammed gate array is an array of b a s ic c e lls . Thus the "gates" in a gate array are , F-Macros are created and offered by Fujitsu to emulate the function of popular industry-standard TTL , determined by the location on the chip of the associated circuitry and any pin location requirements that may , duplicate the function of many popular industry-standard TTL devices and RAM macros which provide from 1K to , Fujitsu' s F-M acros are direct software macro implementations of popular Industry-standard TTL functions
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full adder using ic 74138 full adder using Multiplexer IC 74151 pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 circuit diagram for IC 7483 full adder DN 74352 MB65XXXX MB66XXXX MB67XXXX C4002

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC hardware platform for a multitude of high performance systems previously requiring TTL, Schottky TTL and , 48mA per pin by means of parallel bond wires within the package. It should be remembered that an I/O , . Schmitt trigger input cells offer 1.2V of hysterisis for CMOS levels and 0.7V for TTL levels. More details , , leadless and leaded chip carriers (quad flat pack) and pin grid arrays. The selection of a suitable package , most common interface points are unsimulated logic diagram or simulated netlist though, of course, many
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74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder

16CUDSLR

Abstract: 7474 D flip flop free PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s M u , , arithm etic and relational op eration s D elay p red iction and tim ing an aly sis fo r g ra p h ic an d , create, verify, and program com p lex logic d esig n s. Figure 1 sh o w s a b lock d iagram of M A X +P L U S . Figure 1. MAX+PLUS Block Diagram MAX+PLUS Design Processing (Compiler) T h e P L D S-M , ith a variety of d esign entry m ethods. M A X +P L U S su p p orts hierarch ical en try o f b oth G
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7474 D flip flop free alu 74382 sn 74373 pin diagram of ic 74190 counter schematic diagram 74161 ALU IC 74381

M5L8042

Abstract: panasonic inverter dv 707 manual PROMs? IC MASTER provides the most complete listing of application notes available in print. It is easy , PROMs. If he knows the device number, he can look it up in the part number index at the front of IC , provided by IC manufacturers and pick the most appropriate device. Literally hundreds of pages of , capability of manufacturers to perforr STD-883 screening and high-reliability testing. ®IC MASTER 1985 , 3527-1 Character Generators 4107-1 TTL 846-101 Chimes 3525-52 ®IC MASTER 1985 13 TER SELECTION GUIDE
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M5L8042 panasonic inverter dv 707 manual ccd camera mc 7218 wiring diagram tmm2114 tda 12011 Toshiba DC MOTOR DGM 3520 2A J26487 S-17103 54070Z CH-5404

A5 GNC mosfet

Abstract: SL1626 may be reproduced without express written permission of the publishers. Copyright IC MASTER, 1977. IC , , the IC MASTER directory also provides the first industry wide purge of obsolete material. Application , - plete alphanumeric listing of each company's iC standard product line. Adjacent page number references , this vast body of infor-UPDATES mation is constantly refreshed. Your guarantee that the iC MASTER will , information you need to use the AMI 6800 microprocessor family of circuits in microcomputer systems. (156
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A5 GNC mosfet SL1626 HA1452 ABB inverter motor fault code TCA345 INTERSIL application bulletin AMI6800H AMI6800 VMI6800
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