500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
SN7414NSRE4 Texas Instruments 7414 SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, SOP-14 visit Texas Instruments
SN7414DE4 Texas Instruments 7414 SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14 visit Texas Instruments
SN7414DRG4 Texas Instruments 7414 SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14 visit Texas Instruments
SN7414DRE4 Texas Instruments 7414 SERIES, HEX 1-INPUT INVERT GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14 visit Texas Instruments
SN7414N3 Texas Instruments Hex schmitt-trigger inverters 14-PDIP 0 to 70 visit Texas Instruments
SN74145NSRE4 Texas Instruments TTL/H/L SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16 visit Texas Instruments

pin diagram of 7414

Catalog Datasheet MFG & Type PDF Document Tags

5082-7414

Abstract: HP 5082-7415 Pin Description PIN NO. 5082-7402/741 J! FUNCTION 5082-7403/7413 FUNCTION 5082-7404/7414 FUNCTION , 937. Mechanical The 5082-7400 series package is a standard 12 or 14 Pin DIP consisting of a plastic , INTENSITY Assures Uniformity of Light Output from Unit to Unit within a Single Category â'¢ IC COMPATIBLE , located on the back side of the package. 4. Time for a 1 0%-90% change of light intensity for step change , ) (.100) TYP. Figure 5. 5082-7402/-7403/-7401/ -7412/-7413/-7414 wwwir _0.51 f 4.45 (.020
-
OCR Scan

ls14

Abstract: functions as an inverter, but because of the Schmitt action, it has different input threshold levels for , triggered from the slowest of input ramps and still give clean, jitter-free output signals. 1 14 2 , 7414 LS14 SNJ54LS14FK â'  Package drawings, standard packing quantities, thermal data , important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright ï
Texas Instruments
Original
ls14 SN5414 SN54LS14 SN7414 SN74LS14 SDLS049B SN7414N

ka2201

Abstract: class h power amplifier hi power schematic  SAMSUNG SEMICONDUCTOR INC TS DE§ 7^4142 â¡â¡03ÃS3 2 KA2201/N LINEAR INTEGRATED CIRCUIT 1.2W AUDIO POWER AMPLIFIER TheKA2201/Nis a monolithic integrated audio amplifier in 8 pin plastic dual , current (lcc=4mA: Typ). â'¢ Good ripple rejection. . â'¢ Minimum number of external parts required. SCHEMATIC DIAGRAM Fig. 1 SAMSUNG SEMICONDUCTOR 70 SAMSUNG SEMICONDUCTOR INC Tfl DEf 7cibm4a â¡0D3fiS4 4 , /O), FEEDBACK RESISTANCE SAMSUNG SEMICONDUCTOR 72 SAMSUNG SEMICONDUCTOR INC Tà DE~| 7^414 3
-
OCR Scan
ka2201 class h power amplifier hi power schematic KA2201-N Harmonic pin diagram of 7414 samsung power supply schematic T--14

pin diagram of 7414

Abstract: f574 . Use suffix = SJX. Logic Symbols Connection Diagram Pin Assignment fo r DIP and SOIC 0E- 1 , has inverted outputs. Features Inputs and outputs on opposite sides of package allow easy , 7-413 I 564 Unit Loading/Fan Outl Pin Names See Section 2 for U .L definitions 74F , Outputs Functional Description The 'F564 consists of eight edge-triggered flip-flops with in dividual , flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and
-
OCR Scan
f574 74F564 74F564PC 74F564SJ 74F10

pin diagram of sn74ls14n

Abstract: because of the Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT­) signals. These circuits are temperature compensated and can be triggered from the slowest of , SNJ54LS14W SNJ54LS14FK TOP-SIDE MARKING SN7414N SN74LS14N 7414 LS14 SN7414 LS14 SN5414J SNJ5414J SN54LS14J , important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright
Texas Instruments
Original
pin diagram of sn74ls14n SN7414D SN7414DR SN74LS14D SN74LS14DR SN7414NSR SN74LS14DBR

KM68V257CP

Abstract: 28-DIP-300 300mil 28-pin plastic DIP or SOJ FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION (ToP views) CLK GEN. Préchargé Circuit t 1 1 Vcc Vss l'02 QJ l/Oa[i3 Vss[l4 Pin Name Pin Function A0-A14 Address Inputs , '¢ Standard Pin Configuration - KM68V257CP : 28-DIP-300 - KM68V257CJ : 28-DIP-300 GENERAL DESCRIPTION The , KM68V257C uses eight common input and output lines and has an output enable pin which operates faster than , Manufacturer KM68V257C CMOS SRAM ABSOLUTE MAXIMUM RATINGS* Item Symbol Rating Unit Voltage on Any Pin
-
OCR Scan
KM68V257C-15 KM68V257C-17 KM68V257C-20

MwT-22Q4

Abstract: ATC100a101 intercept performance of the MwT-22Q4 is excellent, typically 14 dB above the 1 dB power gain compression , 1200 650 -1.2 V -8.0 -12.0 V -12.0 -14.0 °C/W Outline Diagram MicroWave , °C)* SYMBOL Vds Vgs Ids Igs Pdiss Pin max Tch PARAMETERS Drain-Source Voltage , Storage Temperature ºC -65 to 150 *Operation of this device above any one of these parameters may , details of matching circuits. Typical Scattering Parameters: (Vds=7.5V, Ids=550mA, Ta =25°C
Microwave Technology
Original
MwT-22Q4 ATC100a101 ATC200B104 ATC700a ATC700A102 MWT22Q4 T-22Q4 DC-4000 TRL10

112 pin cache

Abstract: CYM7424 CYM7425 CYPRESS Package Diagram 112-Pin Dual-Readout SIMM PM11 h â'" .380 MAX â , C Y M 7414 â'"^ r # C Y PR ESS CYM7425 = ^ ^ = = = ^ ^ ^ ^ , Description Features Each module interfaces with the rest o f the system via a 112-pin Burndy connec , -4) substrate. The package dimensions are 3.145" x 0.380" x 1.105". All inputs and outputs of the CYM7424 and , are plated with 100 micro-inches of nickel covered by 10 micro-inches o f gold flash. These
-
OCR Scan
112 pin cache 128K/256K 82420EX CYM7425PB 112-P

pin diagram of 7414

Abstract: pin 7 diagram of 7414 suited for use in high-density high-speed system applications. The KM64B1003 is packaged in a 400 mil 32-pin plastic SOJ. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION (Top views) Pin Name Pin Function Ao-A,7 , â'¢ Center Power/Ground Pin Configuration â'¢ Standard Pin Configuration KM64B1003J : 32 , enable pin which operates faster than address access time at read cycle. The device is fabricated using , Rating Unit Voltage on Any Pin Relative to VBs V|N, VoLTT -0.5 to 7.0 V Voltage on Vcc Supply Relative
-
OCR Scan
KM64B1003J-10 KM64B1003J-12 KM64B1003J-15 pin 7 diagram of 7414 KM6481003J-8 32-SQJ-400 71L4142

FMM5056VF

Abstract: 005s11 V DC Input Voltage VGG -7 V Input Power Pin 12 dBm Tstg -55 to +125 Symbol Condition Unit VDD 10 V Input Power at Tc=25 Pin 10 dBm DC Input , at Pin=-5dBm ESD - 1 FMM5056VF 5.8-7.2GHz Power Amplifier MMIC OUTPUT POWER , POWER ADDED EFFICIENCY vs. INPUT POWER VDD=10V, VGG=-5V VDD=10V, VGG=-5V Pin=+11dBm 36 36 34 34 P1dB 32 Output Power [dBm] Output Power[dBm] 40 30 Pin=+3dBm 28 32 30
Fujitsu
Original
005s11 154-12 power amplifier mmic fujitsu power amplifier GHz FCSI0202M200
Abstract: functions as an inverter, but because of the Schmitt action, it has different input threshold levels for , triggered from the slowest of input ramps and still give clean, jitter-free output signals. 1 14 2 , 7414 LS14 SNJ54LS14FK â'  Package drawings, standard packing quantities, thermal data , important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright ï Texas Instruments
Original
SNJ5414 ISO/TS16949

pin diagram of 7414

Abstract: 7414 fast applications. The KM68257C is packaged in a 300 mil 28-pin plastic DIP or SOJ. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONfrop view) CLK GEN Pre-charge Circuit t i I Pin Nam« Pin Function Ao-Au Address Inputs we Write , '¢ Fully Static Operation - No Clock or Refresh required â'¢ Three State Outputs â'¢ Standard Pin , input and output lines and has an output enable pin which operates faster than address access time at , CMOS SRAM ABSOLUTE MAXIMUM RATINGS * Item Symbol Rating Unit Voltage on Ariy Pin Relative to Vss
-
OCR Scan
KM68257C-12 KM68257C-15 KM68257C-20 KM68257CJ 7414 fast TTL 7414 data KM68257CP-15 KM68257CP 28-SQJ-300

FMM5056

Abstract: FMM5056VF Symbol VDD VGG Pin Tstg Rating 12 -7 12 -55 to +125 Unit V V dBm Recommended Operating Condition , Temperature Symbol VDD Pin IDD Tc Condition 10 10 1200 -40 to +85 Unit V dBm mA ELECTRICAL CHARACTERISTICS , dBm dB dB mA mA CASE STYLE: VF Note: G1dB is referenced to Linear Gain measured at Pin , Power [dBm] 5.8GHz 6.4GHz 7.2GHz 40 Power Added Efficiency [%] Pin=+11dBm P1dB 35 30 25 20 15 10 5 0 32 30 28 26 24 22 20 -10 Pin=+3dBm Pin=-5dBm -5 0 5 10 15 Input Power
Eudyna Devices
Original
FMM5056

HCPL-3700 Application note 1004

Abstract: varistor xf 075 in a single eight pin plastic dual in-line package. As shown in the block diagram of Figure 1, this device con- DC+INPUT Vcc Figure 1. Block Diagram of the HCPL-3700 sists of a full-wave bridge rectifier , trigger gate (7414). In the earlier ac application of the HCPL-3700 (limit switch example), a single , -3700 Schmitt Trigger Upper Threshold Voltage of TTL Gate (7414) Output Pullup Resistance Output Filter , Sensing For Industrial _. . _ _ . Vr._ _" . â  . INTRODUCTION The use of electronic logic
-
OCR Scan
HCPL-3700 Application note 1004 varistor xf 075 zener diode cross reference working of ic 7414 IC 7414 not gate with schmitt trigger MC6821

SN7414

Abstract: sn7414 circuit Immunity SN&414, SN 54LS14 J OR W PACKAGE S N 7414 . . . N PACKAGE SN 74LS14 . D OR N PACKAGE (TOP VIEW , 4A 8 D 4Y description Each circuit functions as an inverter, but because of the S chm itt action , ) signals. These circuits are tem perature-com pensated and can be triggered from the slowest of input ramps , characterized for oper ation over the full military tem perature range of -5 5 ° C to 1 2 5 °C . The S N 7 4 1 4 , accordance w ith ANSI/IEEE Std 9 1 -1 9 8 4 and IEC Publication 617 -12 . Pin numbers show n are fo r D, J, N
-
OCR Scan
sn7414 circuit SN414

5953-0406E

Abstract: IC 7414 not gate with schmitt trigger in-line package. As shown in the block diagram of Figure 1, this device consists of a full-wave bridge , INPUT IO D3 D4 VO 6 4 3 DC­ INPUT Figure 1. Block Diagram of the HCPL-3700 5 GND , output of the optocoupler is interfaced to a TTL Schmitt trigger gate (7414). 360 320 , few. The plastic 8 pin DIP package is designed to be operated over a temperature range of -25°C to , + RL CL C TH+ TH­ PRX PIN PA t+ t­ T CP = Positive Supply Voltage = Input Resistance of
Avago Technologies
Original
5953-0406E OPTOCOUPLER 3700 optocoupler with schmitt trigger input optocoupler PC 187 HCPL3700 IC 7414 datasheet

AD7414-1

Abstract: AD7414 addresses for the AD7414. 2. SM Bus/I2C Compatible Serial Interface with pin selectable choice of three , 0.25oC resolution. 2 IN T E R F A C E 6 3. Supply voltage of 2.7V to 5.5V. 4. Space saving 6-Pin , . Diagram for Serial Bus Timing ­2­ REV. PrA Preliminary Technical Data AD7414 AD7415 PIN , -40oC to +85oC Accuracy of ±2oC SM BusTM/I2CR Compatible Serial Interface 25uA Supply Current Space Saving 6-pin SOT-23 Package Pin-Selectable Addressing via AS Over Temperature Indicator SMBus alert
Analog Devices
Original
AD7414-1 AD7414-0 AD7414ART-0REEL AD7414ART-0REEL7 AD7414ART-1REEL7 AD7414ART CHA
Abstract: ELEC T R O N IC S â  7^414? 00550S5 flfll â  PRELIMINARY KS0787 PIN. NO. CMOS , . The techology o f this device is used high voltage C-MOS Si gate, is packed 191-pin S-TAB(Slim-Tape , ±10% ) : MAX-32V(-34V) : MAX 8 MHz (6.5MHz) â  191-PIN S-TAB(SLIM-TAPE AUTOMATED BONDING) â C-MOS , CMOS DIGITAL INTEGRATED CIRCUIT KS0787 BLOCK DIAGRAM VDD VSS , 5 3 TOT â  PRELIMINARY KS0787 CMOS DIGITAL INTEGRATED CIRCUIT PIN DESCRIPTION 1 -
OCR Scan
191-PIN Y1-Y160 D0220 60-QFP-UUA 64-QFP-1420D Q0550

OTA5180A

Abstract: HDIR(pin) = â'Lowâ' : The definition of HDIR register setting is inversion from original. HDIR , . (Default of the Register) (VDDIO) HDIR(pin) = â'Highâ':The definition of HDIR register setting is , the register setting : VDIR) VDIR I VDIR(pin) = â'Lowâ': The definition of VDIR register , '1â': Shift from down to up. (Default of the Register) (VDDIO) VDIR(pin) = â'Highâ': The definition of , write mode when set to â'˜0â'™. Read M ode: W riting to address register & Setting of SDA pin in
Newhaven Display
Original
OTA5180A 480RGB

HC000

Abstract: AN1178 . Top Level Block Diagram of M8813F2x M8813F2x PLD Bus 32 KByte Boot Flash 4 sectors CPLD , AN1178 APPLICATION NOTE 80C51 / M88 FLASH+PSD Design Guide The M88x3Fxx devices are members of ST's M88 FLASH+PSD family of flash-based peripherals for use with embedded microcontrollers (MCUs). These Programmable System Devices (PSDs) consist of memory, logic, and I/O. When coupled with a , ISP easy, regardless of how much experience you have with embedded design. This document offers two
STMicroelectronics
Original
HC000 AN1171 PSD an1171 AN1153 PSD AN1153 80C51XA 80C51-
Showing first 20 results.