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TLC2934PWR Texas Instruments PHASE DETECTOR, 130MHz, PDSO14, PLASTIC, TSOP-14 visit Texas Instruments
TLC2934PW Texas Instruments PHASE DETECTOR, 130MHz, PDSO14, PLASTIC, TSOP-14 visit Texas Instruments
TLC2934PWLE Texas Instruments PHASE DETECTOR, 130MHz, PDSO14, PLASTIC, TSOP-14 visit Texas Instruments
ISL8702IBZ Intersil Corporation Adjustable Quad Sequencer; SOIC14; Temp Range: -40° to 85°C visit Intersil Buy
ISL6124IRZA Intersil Corporation Power Sequencing Controllers; QFN24; Temp Range: -40° to 85°C visit Intersil Buy
ISL8702IBZ-T Intersil Corporation Adjustable Quad Sequencer; SOIC14; Temp Range: -40° to 85°C visit Intersil Buy

phase sequence detector

Catalog Datasheet MFG & Type PDF Document Tags

phase sequence detector

Abstract: HSP50210 pin 52) signal can be used to streamline the "read the lock detector" sequence. On the evaluation , . The processor control command sequence required for this mode is: 1. Initialize the Lock Detector , GAIN ACCUMULATOR (8 MSBs) (W000)1 A0-2 32 READ HOLDING REG'S 4. LOCK DETECTOR PHASE , THRESHOLD REGISTER AGC LOOP PARAMETERS CARRIER PHASE ERROR DETECTOR FREQUENCY DETECTOR FREQUENCY ERROR , 2. Start the Lock Detector. 3. Set the Read Address for a Phase Error or Gain Error Read. 4. Read
Intersil
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phase sequence detector

Abstract: HSP50210 pin 52) signal can be used to streamline the "read the lock detector" sequence. On the evaluation , . The processor control command sequence required for this mode is: 1. Initialize the Lock Detector , ACCUMULATOR (8 MSBs) (W000)1 A0-2 32 READ HOLDING REG'S 4. LOCK DETECTOR PHASE ERROR , REGISTER AGC LOOP PARAMETERS CARRIER PHASE ERROR DETECTOR FREQUENCY DETECTOR FREQUENCY ERROR DETECTOR , 2. Start the Lock Detector. 3. Set the Read Address for a Phase Error or Gain Error Read. 4. Read
Intersil
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three phase sequence detector

Abstract: phase sequence detector phase detector. The reference divider is a fully programmable 13-bit asynchronous design and can b e se , allowing use of an external phase detector. There are three further control bits associated w ith the phase , bit controls the sense o f the phase detector, allowing for inversions o f control direction in the , parameters (see Table 1). MSB 0 0 LSB 0 Digital Analog Output for RF phase lag Sense bit Digital detector , divider A and M counters using 19-bits, the phase detector gain w ith tw o bits and the phase detector
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Abstract: 84873027 Control of 3-phase networks : phase sequence, phase failure Multi-voltage True RMS measurement , Functions Nominal voltage (V) HWTM Phase sequence, phase failure, motor temperature via PTC probe , functions are independent of one another. The 3-phase (208 to 480 V) network control verifies the sequence , /2014 www.crouzet.com Control of 3-phase network As soon as the phase sequence (L1 L2 L3) and , in the amplitude of a phase (absence of phase with regeneration) or inversion of the phase sequence Crouzet
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phase sequence detector

Abstract: three phase sequence detector   Integrated Analog and Digital Phase Detectors â  Programmable Phase Detector Gain H Power Down Mode â , is the reference source for the phase detector. The reference divider is a fully programmable 13 , allowing use of an external phase detector. There are three further control bits associated with the phase , programmable divider A and M counters using 19-bits, the phase detector gain with two bits and the phase , . Output for RF phase lag Sense bit Digital detector Analog detector 0 1 Current source Current sink
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phase sequence detector

Abstract: discrete phase sequence detector Right sequence GP2 GP4 Phase A Phase B Phase C Zero Detector GP0 Zero Detector , right sequence of phase occurrence is done as a software task of temporary majority identification, which is well known in microcontroller practice. When the sequence of phases is correct, the PIC , Discrete Logic Replacement Sequencer Phase Control Author: DESCRIPTION George Hristov Sofia, Bulgaria The presented circuit checks for the right sequence of phases (A, B, C). In the
Microchip Technology
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Abstract: reference divider whose output is the reference source for the phase detector. The reference divider is a , and reference divider signals switched to output pins allowing use o f an external phase detector , buffer. The SP8850 first bit controls the sense of the phase detector, allowing for inversions of , and M counters using 19-bits, the phase detector gain w ith two bits and the phase detector sense , local oscillator divider words. Analog and digital phase com parators are provided and both gain and -
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Three phase oscillator

Abstract: pan 9730 programmable reference divider whose output is the reference source for the phase detector. The reference , signals switched to output pins allowing 3 use of an external phase detector. There are three further , iia ii^ /c s c* v c p I« llW Output for RF phase lag Sans* bit u Digital detector current souroe , M counters using 19-bits, the phase detector gain with two bits and the phase deloctor sense with , '-' * i w imlui \ C lr 7 0 r · uo SP8850 PHASE detector OAIN CONTROL
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Three phase oscillator pan 9730 SP08SO 28-LEAD 602358F

sds ts2

Abstract: 32D532 EPD ENABLE PHASE DETECTOR: A low level (Coast Mode) disables the phase detector and allows the VCO to , XTAL2 open. The frequency must be at twice the data rate. PD OUT PHASE DETECTOR OUTPUT: Drives the , frequency, the phase detector gain, and the 1/4 cell delay. The value of this resistor is given by: RR = , employs a dual mode phase detector; harmonic in the Read mode and non-harmonic in Write and Idle modes. In the Read mode the harmonic phase detector updates the PLL with each occurrence of a DLYD DATA pulse
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32D532 sds ts2 rll to nrz AIC-010 ST506 AIC010 35TSA 28-PIN SSI32D532CH

TRANSISTOR W2T

Abstract: Transistor W2T 58 oscillator divider words. A digital phase detector with two charge pumps, programmable in phase and gain, are , -40°C to+85°C (B grade). FEATURES â  Improved Digital Phase Detector Eliminates 'Dead Band' Effects ,   Programmable Phase Detector Gain â  Power Down Mode O X U o Fref*[ power down [ Vee4[ Vcc4[ Veci [ rf , phase detector sense bit in the F1 /F2 programming word. The above diagram is correct when the sense bit , n15 single 13 bit 1 bit 2 bit reference buffer logic V V phase detector charge
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SP8853 TRANSISTOR W2T Transistor W2T 58 phase detector 3GHz discrete phase sequence detector 7AF1 phase detector SP8853A/B DS2352 418/ED/39501/009 GPD00281 418/ED/51186/001

three phase sequence detector

Abstract: 11C44 Testing Fig. 2 Short Sequence* tor Phase/Frequency Detector Testing INPUTS RF 0 0 1 1 VF 0 1 0 1 , 11C44 PHASE/FREQUENCY DETECTOR 11 COO S E R IE S GENERAL D ESC RIPTIO N - The 11C44 contains a Phase/Frequency Detector, a Phase Dectector, a Charge Pump, and an Am plifier. The Phase/Frequency , have the same frequency, the Phase Detector outputs U2 and D2 provide binary signals whose duty cycles , VF - Variable Frequency Input U1, D1 - Phase/Frequency Detector Outputs U2, D2 - Phase Detector
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three phase sequence detector 11C44DC PHASE LEAD LAG DETECTOR IC MC4044/4344 MC4044 R3200B

hard drive CIRCUIT diagram

Abstract: which sets the VCO center frequency, the phase detector gain, and the 1/3 cell delay. The value of this , dual mode phase detector; harmonic in the read mode and non-harmonic in the write and idle modes. In the read mode, the harmonic phase detector updates the PLL with each occurrence of aDLYD DATA pulse. In the write and idle modes, the non-harmonic phase detector is continuously enabled, thus , the read mode the falling edge of DRD enables the phase detector while the rising edge is phase
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hard drive CIRCUIT diagram 32D539
Abstract: Programmable phase detector gain for dualband operation n CDMA (IS-95) n Programmable phase , Charge Pump Leakage Currentâ'  â'" â'" 0.1 20 nA Phase Detector Noise Floor (±150 Hz , pump disable function. Programable charge pump current for frequency band 2. Phase detector polarity , . D5â'"Phase Detector Polarity (Bit 17) D5 Phase Detector Polarity 0 Negative 1 Positive The phase detector can be programmed for either a negative or positive slope to accommodate the VCO and low Lucent Technologies
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W3000 GSM900/DCS1800/PCS1900 IS-136/137 RCR-27 RCR-28 GSM900

XR-532A

Abstract: XR532 Control Gain Phase Detector Gain KVCO x KD Product Accuracy VCO Phase Restart Error Decode Window , here determines the one-shot timer period used for synchronization detection. Phase Detector Enable. When low, the VCO free-runs. When high, the VCO receives the phase detector control voltage. Internal pull-up resistor provided. VCO Input Control Voltage. Phase Detector control voltage applied here , Description Phase Detector Output. The PLL filter placed here conditions the phase detector output before
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XR-532A XR-532ACQ XR532 xr532acj 40670 ic 474 XR-532ACJ

XT pll 10mHZ

Abstract: XR-532ACJ Detector Gain KVCO x KD Product Accuracy VCO Phase Restart Error Decode Window Centering Accuracy Decode , here determines the one-shot timer period used for synchronization detection. Phase Detector Enable. When low, the VCO free-runs. When high, the VCO receives the phase detector control voltage. Internal pull-up resistor provided. VCO Input Control Voltage. Phase Detector control voltage applied here , PDOUT Description Phase Detector Output. The PLL filter placed here conditions the phase detector
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XT pll 10mHZ XR-532ACD E16-----------------

LA 7687 a

Abstract: LA 7687 IC CIRCUIT Improved Digital Phase Detector to Eliminate 'Dead Band' Effects Low Operating Power, Typically l75mW , giving Rapid Frequency Toggling Programmable Phase Detector Gain Power Down Mode ESD Protection on all , LOCK DETECT 14 DATA 28 Cd Fpd and Fref outputs are reversed by the phase detector sense bit in the , ""V- SINGLE REFERENCE BUFFER \7 1 phase detector charge pomp 1 3 ' PD1 -«-O ERROR ! signal â , programmable reference divider whose output is the reference for the phase detector. The reference divider is a
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LA 7687 a LA 7687 IC CIRCUIT LA 7687 A IC CIRCUIT SP6853 la 7687 transistor dg28 800MH X1000 687X10 318X10 X10-4 53X10-8

Marconi 2030

Abstract: MARCONI 2031 resolution of such a synthesizer is limited by the phase detector rate - if a 1 kHz phase detector rate is , Generator (Fig. 2) to provide 10 Hz resolution based on a phase detector rate of 40 kHz. An accumulator , value on each cycle of the phase detector clock. The residual phase error in the PLL also accumulates in , phase detector. Changing the division ratio by one for one cycle of the phase detector effectively , detector rate) and a phase change (or time change) at the detector has a different phase impact on the VCO
Aeroflex
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Marconi 2030 MARCONI 2031 MARCONI 2965 MARCONI radio test set microwave MARCONI marconi 2022

32d5362

Abstract: 32D5362A . This resistor establishes a reference current which sets the VCO center fre quency, the phase detector , the Phase Detector while the rising edge is phase com pared to the rising edge of the VCO/2. As , delay only affects the retrace angle of the phase detector and does not influence the accuracy of the , reference may be applied to XTAL1, leaving XTAL2 open. The SSI 32D5362A employs a Dual Mode Phase Detector , Non-Harmonic Phase Detector is con tinuously enabled, thus maintaining both phase and frequency lock. By
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32d5362 32D536 c5622 32C452 32D5362A-CP 32D5362A-CH

LA 7687 a

Abstract: feature. 1 c/ c [ 8E I â  M M H H H H â  M Improved Digital Phase Detector to , Programmable Phase Detector Gain Power Down Mode ESD Protection on all Pins HP28 'U U U U U U U ' 15 , LOCK DETECT Cd Fpd and Fref outputs are reversed by the phase detector sense bit in the , divider whose output is the reference for the phase detector. The reference divider is a fully , options are shown in table 4. An external phase detector may be connected to pins 4 and 5 and may be
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SP8861 41627Q 318X1Q

ST506

Abstract: c28h delays, WCLK may be connected directly to pin RRC (Read/Reference Clock). ENABLE PHASE DETECTOR: A low level (Coast Mode) disables the phase detector and allows the VCO to coast. Pin EPD has an internal , OUT PHASE DETECTOR OUTPUT: Drives the Loop Filter input. VCO IN VCO CONTROL INPUT: Driven by the , reference current which sets the VCO center frequency, the phase detector gain, and the 1/4 cell delay. The , to XTAL1, leaving XTAL2 open. The SSI 532 employs a dual mode phase detector; harmonic in the Read
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c28h htrw SSI532 532-C28H 532C28P
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