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CS2000P-CZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-CZZR Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-DZZR Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-CZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000P-CZZR Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-DZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10

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pecl clock so8

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Intended application LQFP-32 HVQFN-32 high-performance PECL clock distribution synchronous output enable SO-20 TSSOP-20 high-performance PECL clock distribution synchronous output enable; LVDS input compatible SO-20 TSSOP-20 high-performance PECL clock distribution LQFP-32 HVQFN-32 high-performance PECL clock distribution individual output enable; LVPECL input , -52 300 -40~+85 LQFP-52 high-performance PECL clock distribution 300 300 -40~+85 Philips Semiconductors
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LCD 09151 SC28L198 CSOT109 PCF8591 APPLICATION PCK2002 PCF8582C-2 PCA9564 P82B96 P82B715 LM75A
Abstract: manufacturer of advanced, high performance communications, clock management, mixed signal, analog and power , product family includes precision frequency synthesizers, clock distribution and translation, multiplexers , low-data-rate RF communications to a system. The tiny SO-8 receivers require just three external components to , Adj. 3.0, 3.3, 5.0 3.3, 4.85, 5.0, 5.0 (0.5%) 3.0, 3.3, 4.85, 5.0 SO-8 Package, JA = 160 , 16V SO-8 Package, JA = 160°C/W 2.5V to 16V 48uA 48uA 48uA 48uA 48uA 100uA Micrel Semiconductor
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SOP8 8002 Amplifier SCR s838 TRANSISTOR s838 4606 MOSFET INVERTER transistor SMD DK QB Marking Code SMD CM sot-23-5 M-0009
Abstract: -16 Imod/Bias [mA] EAM [Vppse] Dual Loop 2,5 3,5 3,5 3,5 X X X CML/PECL CML/PECL CML/PECL CML/PECL CML/PECL CML/PECL CML/PECL CML/PECL CML/PECL 0.5Vse 0.5Vse 0.5Vse , analog PECL PECL CML/PECL CML/PECL CML Sens [mV] BER Flag Loop filter X 2,5 2,5 X X internal internal CML CML CDR Clock Conversion Frame D/Align Buswidth X X 4/8 32 32 4/8/10/16 4/8/10/16 PECL/TTL CML/TTL CML/GTL CML/LVPECL CML/LVPECL Philips Semiconductors
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TZA3033 TZA3023 TZA3043 TZA3013 CGY2110 LQFP48 HTQFP100 DB4042 HBCC32 BICMOS MSD818 CGY2102
Abstract: SO16 SO16 SO16 SO16 LQFP48 LQFP 32 LQFP 32 LQFP 32 LQFP48 SO8 LQFP 32 SO8 LQFP 32 SO8 LQFP 32 SO8 2488 OQ2541 LQFP48 LQFP48 2488 2488 , X X X X X X X X X Bare Die X Clock conversion 2.5 2.5 , AND CLOCK RECOVERY 155 NE/SA5224 LIMITING AMPLIFIER 622 TZA3031 LASERDRIVERS 622 , Level detect X X X E.R. control X X LP Filter CML/GTL CML/TTL PECL/TTL -
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TZA3001 OQ2545 TZA3004 TZA3034 TZA3005 TZA3030 9952 10 gb laser diode TZA3041 CGY2111 OQ2535 OQ2536
Abstract: PECL PECL CML/PECL CML/PECL CML BER Flag Loop filter X X internal internal Clock Conversion X Frame D/Align X Buswidth PECL/TTL CML/TTL CML/GTL CML/LVPECL/LVDS CML/LVPECL , TZA3034 TZA3044 TZA3014 TZA3019 OQ2538 155 1250 3250 3250 2488 CLOCK AND DATA RECOVERY , . Control 60/90 60-90 60-90 80-100 60-100 - 2,5 3,5 3,5 3,5 X X X X CML/PECL CML/PECL CML/PECL CML/PECL CML/PECL 0.5Vse 0.5Vse 0.5Vse BW [MHz] Level detect 2 2 Philips Semiconductors
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LQFP32 TZA3012 CGY2151 cgy2141 CGY2140 OQ2541/B TZA3017 SO16/TSSOP16
Abstract: Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE , MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground , it ideal for applications which require the translation of a clock and a data signal. http://onsemi.com MARKING DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 HLT22 ALYW 1 1 8 KLT22 ALYW · · · · · · 1.2 ON Semiconductor
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ELT22 MC100 AND8002/D MC10ELT22D MC10ELT22DR2 MC100ELT22D
Abstract: Supports DC to 625 MHz operation HSTL compatible differential clock outputs PECL compatible differential , -lead Pb-free package available MC100ES8011P 1:2 DIFFERENTIAL PECL TO HSTL CLOCK FANOUT DRIVER D SUFFIX , ]) Figure 3. MC100ES8011P AC Reference Measurement Waveform (PECL Input) MC100ES8011P 4 Advanced Clock , Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock fanout buffer. Designed for the most demanding clock distribution systems, the Freescale Semiconductor
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MC100ES8011PD MC100ES8011PDR2 MC100ES8011PEF MC100ES8011PEFR2
Abstract: SHEET Product Preview Low Voltage 1:2 Differential PECL Clock Fanout Buffer MC100ES7011P MC100ES7011P The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock fanout buffer. Designed , clock outputs PECL compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package 1:2 DIFFERENTIAL PECL TO LVDS CLOCK FANOUT DRIVER D , PECL Clock Fanout Buffer MC100ES7011P 746 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA Integrated Device Technology
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Integrated Device Technology CROSS MC100ES7011PD MC100ES7011PDR2 MPC92459 AN1091 MC100ES6011 199707558G
Abstract: MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. http , Loading SO-8 D SUFFIX CASE 751 Flow Through Pinouts 1 KLT22 ALYW G 1 Operating Range , . PIN DESCRIPTION Q0 1 8 VCC Pin Function Qn, Qn 2 PECL D0 TTL TTL Inputs ON Semiconductor
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HT22 MC10ELT22/D
Abstract: Product Preview Low Voltage 1:2 Differential PECL Clock Fanout Buffer The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock fanout buffer. Designed for the most demanding clock distribution , Supports DC to 1000 MHz operation LVDS compatible differential clock outputs PECL compatible differential , MC100ES7011P 1:2 DIFFERENTIAL PECL TO LVDS CLOCK FANOUT DRIVER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 , differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very Freescale Semiconductor
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Abstract: Product Preview Low Voltage 1:2 Differential PECL Clock Fanout Buffer The MC100ES7011P is a low voltage 1:2 Differential PECL to LVDS clock fanout buffer. Designed for the most demanding clock distribution , Supports DC to 1000 MHz operation LVDS compatible differential clock outputs PECL compatible differential , MC100ES7011P 1:2 DIFFERENTIAL PECL TO LVDS CLOCK FANOUT DRIVER D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 , differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very Freescale Semiconductor
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Abstract: MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. MARKING , Through Pinouts Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V SO-8 D SUFFIX CASE 751 No , Pin Function Qn, Qn Q0 2 PECL Dn VCC D0 TTL Q1 3 6 4 5 Positive ON Semiconductor
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ic so8 socket BRD8011/D
Abstract: data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is , DIAGRAMS* 8 1 SO-8 D SUFFIX CASE 751 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 8 HEL35 ALYW 1 8 KEL35 ALYW · · , , > 100 V MM PECL Mode Operating Range: VCC = 4.2 V to 5.7 with VEE = 0 V NECL Mode Operating Range: VCC = , DESCRIPTION PIN J K R CLK Q, Q VCC VEE FUNCTION ECL Input ECL Input ECL Reset ECL Clock Input ECL Data ON Semiconductor
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KL35 MC10EL35 MC100EL35 MC10EL/100EL35 EIA/JESD78 AND8003/D UL-94
Abstract: SiGe Technology Supports DC to 400 MHz operation HSTL compatible differential clock outputs PECL , SOIC package MC100ES8011P 1:2 DIFFERENTIAL PECL TO HSTL CLOCK FANOUT DRIVER D SUFFIX 8 , Measurement Waveform (PECL Input) 768 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA , Product Preview Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock fanout buffer. Designed for the most demanding clock Freescale Semiconductor
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Abstract: MC10ELT22, MC100ELT22 5VDual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. · · · , Pinouts ESD Protection: >2 KV HBM, >200 V MM Operating Range: VCC= 4.75 V to 5.25 V with GND= 0 V SO­8 , Assembly Location KT22 ALYW 1 L = Wafer Lot Y = Year W = Work Week D0 2 PECL *For ON Semiconductor
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Abstract: which require the translation of a clock and a data signal. The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0 V. · 3.5 , Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE , MC100ELT23 5V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required ON Semiconductor
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KLT23 ELT23 MC100ELT23D MC100ELT23DR2 MC100ELT23DT MC100ELT23DTR2
Abstract: AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at , is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used , . The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAM 8 1 SO-8 D SUFFIX CASE 751 8 KVT20 ALYW 1 · 390 ps Typical Propagation Delay · Maximum Input Clock Frequency , Differential PECL Outputs LVTTL Input Positive Supply Ground No Connect NC 4 5 GND (Top View ON Semiconductor
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AN1642 MC100LVELT20 MC100LVELT20/D AND8020 MC100LVELT20D MC100LVELT20DR2 AN1405/D
Abstract: AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V , MC10ELT22, MC100ELT22 5.0 V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and , makes it ideal for applications which require the translation of a clock and a data signal. http , Loading Flow Through Pinouts Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V SO-8 D SUFFIX ON Semiconductor
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Abstract: which require the translation of a clock and a data signal. The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0 V. · 3.5 , MC100ELT23 5V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required , * 8 SO-8 D SUFFIX CASE 751 1 8 8 1 A L Y W TSSOP-8 DT SUFFIX CASE 948R 1 = Assembly Location = Wafer ON Semiconductor
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MC100ELT23/D
Abstract: applications which require the translation of a clock and a data signal. The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a VCC of 5.0 V , MC100ELT23 5V Dual Differential PECL to TTL Translator The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are , 2 7 Q0 6 MARKING DIAGRAMS* 8 KLT23 ALYW SO-8 D SUFFIX CASE 751 8 1 1 8 ON Semiconductor
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