NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: CONNECTION CONNECTION PIN NO. A. LTS-360 B. LTS-367 C. LTS-368 1 Common Anode *1 Common , ELECTRONIC 2ME D 0035547 ODGGbSG 7 - 33 INTERNAL CIRCUIT DIAGRAM A. LTS-360 B, LTS-367 C. LTS , DESCRIPTION The LTS-360 series are 0.36 inch (9.20mm) height single digit displays. The red series devices , displays have gray face and white segment color. DEVICES PART NO. LTS- DESCRIPTION PACKAGE DIMENSION INTERNAI. CIRCUIT DIAGRAM RED BRIGHT RED GREEN ORANGE HI.-EFP. RED 36QR 360P" 360G 360E 360HR 360HR : Common ... | OCR Scan |
8 pages, |
LTS 543 R lts 543 ic of lts 543 lts 542 7 segment display LTS 542 10 pin common cathode display 7 segment display LTS 543 LTS 542 INTERNAL DIAGRAM LTS 542 10 pin common anode display LTS 542 common cathode pin diagram of LTS 542 7 SEGMENT LT 543 LT 543 common cathode datasheet abstract |
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| Abstract: 2. unless otherwise noted. (0.010") PIN NO. CONNECTION A. LTS-311A B. LTS-312A C. LTS-313A D. LTS-315A B. LTS-316A 1 Anode H Cathode A '. Common Cathode *2 Anode F Anode G.H&J *4 2 No Pin Cathode F - , CIRCUIT DIAGRAM A. LTS-311A B. LTS-312A C. LTS-313A D. LTS-315A r A *t- p- -w- m V 14 13 11 10 9 8 E. , _ 31E_JL - SS3b3b7 QGQS33b MLTN LTS-3Ï0À SERIES 0.3" SINGLE DIGIT NUMERIC DISPLAYS I -3> " , LTS-310A series are 0.3 inch (7.62mm) height single digit displays. The red series devices utilize LED ... | OCR Scan |
12 pages, |
LTS 542 INTERNAL DIAGRAM liteon lt 312 316-AG lts 542 lts 542 pin diagram pin diagram of LTS 542 datasheet abstract |
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| Abstract: ) PIN NO. CONNECTION A. LTS-311A B. LTS-312A C. LTS-313A D. LTS-315A B. LTS-316A 1 Anode H , 6 are internally connected. 4. Pin 1 & 3 are internally connected. 698 J INTERNAL CIRCUIT DIAGRAM , _ 31E_JL - SS3b3b7 QGQS33b ^ BiLTN LTS-3Ï0À SERIES 0.3" SINGLE DIGIT NUMERIC DISPLAYS I -3> " , DESCRIPTION The LTS-310A series are 0.3 inch (7.62mm) height single digit displays. The red series devices , efficiency red displays have red face and red segment color. DEVICES PART NO. LTS- DESCRIPTION PACKAGE ... | OCR Scan |
12 pages, |
pin diagram of LTS 542 313AG 311AG Q002 LTS 542 datasheet abstract |
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| Abstract: in timing diagram of Figure 9). Short Cycle pin connections and associated maximum 12-, 10- and 8-bit , : , Devices. FUNCTIONAL BLOCK DIAGRAM BIT12rrl ILSB FOR 12 BITS! L-L I HEF OUT 6.3V 12-bit accuracy (±0.012% , ADC84/AD ADC84/AD ADC85 ADC85 (10/Lts) and AD5240 AD5240 (5jus) make them an excellent choice for applications requiring high , TEMPERATURE - eC Figure 3b. Gain Drift Error (% FSR) vs. Temperature (AD5240 AD5240) -5-4-2 0+2+4+6+8 +10 +12 +14+16 ... | OCR Scan |
8 pages, |
lts 542 ADC85C ADC85 ADC84 adc interfacing with 8085 AD5240 pin diagram of LTS 542 A0C84/AD ADC85/A05240 MIL-STD-883B A0C84/AD abstract |
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| Abstract: Relation TE Mode, RDY & ECHO pin GCI S-bus Phase Relation NT/LT-S Mode, DE/CEB timing State Diagram of , interface 6.2 SDL Diagram NT 6.3 SDL Diagram LT-S 6.4 SDL Diagram TE, LT-T 6.5 Explanation of Notation , So-interface Configurations : - NT : Network Termination - TE : Terminal Equipment - LTS : Line Termination , XTI Block Diagram XTLO DIN DOUT DFR DCLK ERRATA MTC-20172 MTC-20172 Page 56, Table 6.4.b , . . . . . . . . . 7 3. Pin and Package Data 3.1 3.2 3.3 3.4 3.5 Package and Dimensions . ... | Original |
104 pages, |
MTC20172 ami 6638 fault finding siemens schematic UIC 4102 siemens handbook S1J SIG MTC2071 0.5 MIETEC CMOS MTC-2071 LT 6242 circuit diagram pabx alcatel zkb505 ALCATEL PABX MTC-20172 MTC-20172 abstract |
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| Abstract: the low cost, power consumption, and size/pin count of a 4-bit microcontroller. Therefore, the , language can help bypass code size (and performance) constraints. Figure 2 shows the block diagram of , with acceptable performance and minimum cost. Notably, the pin and interconnect count is radically , P1.0P1.7 P3.0P3.7 OSCILLATOR ADC X1 X2 AVSS AVCC SU00319 SU00319 Figure 2. Block Diagram of , three ports (5-bit port 0, 8-bit ports 1 and 3), are available for user I/O. 8XC752 8XC752 PIN FUNCTIONS ... | Original |
19 pages, |
AN429 LM35 application circuits with LTS-367 lts 542 KP100A LTS 546 lts 547 pin configuration pin diagram of LTS 542 7 segment display 542 application note Seven-Segment Numeric LCD Display seven segment display LTS 543 7 segment display 10 pin LTS 543 lts 542 7 segment display 83/87C752 AN429 83/87C752 abstract |
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| Abstract: Operations & Timing Diagram 1.4.5 Write data mask One write data mask (DM) pin for each 8 data bits (DQ , DDR2 Device Operations & Timing Diagram DDR2 SDRAM Device Operation & Timing Diagram 1 DDR2 Device Operations & Timing Diagram Contents 1. Functional Description 1.1 Simplified State Diagram 1.2 Basic Function & Operation of DDR2 SDRAM 1.2.1 Power up and Initialization 1.2.2 , Pulldown Driver Characteristics 2 DDR2 Device Operations & Timing Diagram 1. Functional Description ... | Original |
62 pages, |
DDR2-800 DDR2-667 DDR2-533 DDR2-400 datasheet abstract |
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| Abstract: input DC - 1 us instruction cycle Device EPROM RAM Pin Diagram PDIP, SOIC VDD GP5/OSC1 , 2nd BCF caused ;GP4 to be latched as the pin value (High). 5.4.2 SUCCESSIVE OPERATIONS ON I/O , Timer0 module is found in Table 6-1. TIMER0 BLOCK DIAGRAM Data bus GP2/T0CKI Pin FOSC/4 0 , PIC12C5XX PIC12C5XX 8-Pin, 8-Bit CMOS Microcontroller Devices included in this Data Sheet: CMOS , Programmable code-protection · Power saving SLEEP mode · Wake-up from SLEEP on pin change · Internal ... | Original |
84 pages, |
USART keypad PIC applications TRANSISTOR SMD MARKING CODE A1 smd transistor kn smd TRANSISTOR code marking 8K smd marking 58a PICDEM-1 PIC16F84 serial connector Zener diode smd marking code .18 454 marking CA 8 pin Zener diode smd marking 27 PIC16 example sleep PIC12C5XX PIC12C508 PIC12C5XX abstract |
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| Abstract: 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB , AC Output Levels 5.4.2 Differential DC & AC Output Levels 5.4.3 Single Ended Output Slew Rate , 6.2 DDR3 Standard speed bins and AC para 7. DIMM Outline Diagram 7.1 512MB 512MB, 64Mx64 Module(1Rank of , in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered ... | Original |
51 pages, |
HMT164S6AFP HMT112S6AFP HMT125S6AFP HMT164S6AFP abstract |
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| Abstract: Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB 512MB, 64Mx64 Module , 5.4.1 Single Ended DC & AC Output Levels 5.4.2 Differential DC & AC Output Levels 5.4.3 Single Ended , Device Density 6.2 DDR3 Standard speed bins and AC para 7. DIMM Outline Diagram 7.1 512MB 512MB, 64Mx64 , SDRAMs in Fine Ball Grid Array(FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered ... | Original |
49 pages, |
DDR3 SODIMM SPD JEDEC HMT164S6AFP HMT112S6AFP HMT125S6AFP HMT164S6AFP abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| -39 5.2.2.3 Timer T0/T1/T2 Run Control Register . . . . . . . . . . . . . . . . . . . . . . 5-42 5 external peripherals." ? Pins using negative logic are indicated by an overbar. For example: "The BYPASS pin is latched with the rising edge of the PORST pin." ? Bit fields and bits in registers are in , groups of signals, or groups of pins are collectively named in the body of the document, they are given pins are given as "NAME[C]" where the range of the variable C is given in the text. For example: CLKSEL www.datasheetarchive.com/files/infineon/mc_data/dave/products/tc1765.dip!/tc1765/documents/tc1765_umpu_v10.pdf |
Infineon | 09/09/2002 | 10835.06 Kb | DIP | tc1765.dip |
| Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1 -23 1.5 Pin Definitions and Functions -12 5.4.2 Software Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 .1.3 DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10 Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 12 Parallel Ports and Pins www.datasheetarchive.com/files/infineon/mc_data/dave/products/tc1765.dip!/tc1765/documents/tc1765_umsu_v10.pdf |
Infineon | 09/09/2002 | 10835.06 Kb | DIP | tc1765.dip |
| .1.5, Section 14.3 summarizes the module interface signals, including pins. Figure 14-2 GPT1 Block Diagram T3 and Destination Pointers . . . . . . . . . . . . . . . . . . 5-22 [1] 5.4.2 PEC Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-80 [1] 8 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2] 22.2.2 Block Diagram register TxCON. Each timer has an input pin TxIN (alternate pin function) associated with it, which serves www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc161cj_v26.dip!/xc161cj/documents/xc161_um_per_v2.1_2003_06.pdf |
Infineon | 25/11/2003 | 8106.77 Kb | DIP | xc161cj_v26.dip |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MC9S12DP256 MC9S12DP256 MC9S12DP256 MC9S12DP256 112-Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . 16 Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MC9S12DP256 MC9S12DP256 MC9S12DP256 MC9S12DP256 112-Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 16 Ordering version of the device. Pins shown in bold on the block diagram and pinout are not available on the 80 Description MOTOROLA MC9S12DP256 MC9S12DP256 MC9S12DP256 MC9S12DP256 112-Pin Block Diagram 256K Byte Flash EEPROM 12K Byte RAM Enhanced KWJ7 Timer Debug Module Note: This block diagram is for the 112-pin version. Pins in bold are not www.datasheetarchive.com/download/20433182-93221ZC/mc9s12dp256_r11.zip (MC9S12DP256.pdf) |
Elektronikladen | 10/03/2002 | 2106.26 Kb | ZIP | mc9s12dp256_r11.zip |
| EBU provides an interface to external peripherals." Pins using negative logic are indicated by an overbar. For example: "The BYPASS pin is latched with the rising edge of the PORST pin." Bit fields and of register fields, groups of signals, or groups of pins are collectively named in the body of the bits, signals, or pins are given as "NAME[C]" where the range of the variable C is given in the text www.datasheetarchive.com/files/infineon/mc_data/dave/products/tc1130.dip!/tc1130/documents/tc1130_umpu_v10d2.pdf |
Infineon | 21/06/2004 | 13980.71 Kb | DIP | tc1130.dip |