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lpddr2 spec

Catalog Datasheet Results Type PDF Document Tags
Abstract: Semiconductor, Inc. 1/? Agenda Industry Trends: IT & Mobile LPDDR2 Effect on Battery Life DDR3 , Industry Trends: IT & Mobile LPDDR2 Effect on Battery Life DDR3 Effect on Energy Saving SSD Effect on , LPDDR2 Effect on Battery Life DDR3 Effect on Energy Saving SSD Effect on Efficiency Virtualization , Memory Bandwidth Wide I/O 12.8GB/s 9.6GB/s LPDDR2 2ch. Serial IO 6.4GB/s LPDDR2 3.2GB/s , Multi Screen `13 `14 Green LPDDR2 Introduction · From Low-density MDDR to higher density LPDDR2 ... Original
datasheet

53 pages,
5818.19 Kb

lpddr2 samsung datasheet samsung ddr2 nand Samsung 8Gb MLC intel lpddr2 mobile lpddr2 samsung toggle ddr2 NAND lpddr samsung lpddr2 Mobile RAM DDR3L lpddr2 samsung SSD samsung ddr3 samsung toggle mode NAND lpddr2 samsung datasheet abstract
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Abstract: BGA (LPDDR, x16) K = 90-Ball BGA (LPSDR, x32) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 5= 220-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) 5 REV 1.0 03 , VDD2 VSS LPDDR2 DQ 3 N/C VDD1 4 N/C N/C 5 N/C N/C 6 N/C N/C 7 N/C N/C 8 N/C N/C 9 , VSSQ DQ30 DQ29 VSSQ DQ26 DQS3_c VDD1 VDDQ DM3 VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3_t LPDDR2 ... Original
datasheet

140 pages,
3075.23 Kb

216-ball lpddr2 spec HYNIX lpddr2 DQ calibration LPDDR2 PoP LPDDR2 1Gb Memory samsung lpddr2 se 094 lpddr2 spec hynix lpddr2 sdram elpida lpddr2 ELPIDA mobile dram LPDDR2 Elpida LPDDR2 Memory hynix lpddr2 NT6TL16M32AQ/ NT6TL32M16AQ NT6TL16M32AQ/ abstract
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Abstract: are supported. I Part No. Category Density I/O Vddl / Vdd2 / Vddq Spec Status» RoHS I W978F6A W978F6A LPDDR2 256Mb X16 1.8V/-/1.2V 200MHz UD (Q3/-I0) Y W978H6A W978H6A LPDDR2 256Mb X16 1.8V/1.2V/1.2V 200MHz UD Y * Status , speed, smaller die size, and DRAM compatible process. Part No. Category Density I/O Vdd/Vddq Spec {Async , /Vddq Spec Status* RoHS I W948D6F W948D6F LPDDR 256Mb X16 1.8V/ 1.8V 200MHz S P(Q1/'10) Y W948D2F W948D2F LPDDR 256Mb , Accountability, Innovation, Teamwork winband We Deliver Low Power DDR2 SDRAM » Mobile LPDDR2 (Low Power Double ... OCR Scan
datasheet

24 pages,
12285.06 Kb

ddr sdram 128Mbit 8Mx16 W968D6D WBGA-84 W25X64V w25x40v winbond ddr sdram 128Mbit 8Mx16 W25X16AV W25Q64CV W25Q32BV application note winbond w25q 8x6mm winbond* W25Q W641GG2IB datasheet abstract
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Abstract: ) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 5= 220-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) 5 REV 1.1 04/2013 4Gb/8Gb LPDDR2-S4 SDRAM NT6TL128M32AI NT6TL128M32AI(Q , DQ17 DQ19 VSSQ DQ21 DQ23 VSSQ VDDQ DM2 VDD2 VSS LPDDR2 DQ 3 N/C VDD1 4 N/C N/C 5 N/C N/C 6 , DQ28 DQ27 VDDQ DQ24 DQS3_t LPDDR2 CA Power Ground Do Not Use ZQ DQS1_c K DM1 VSS DM0 ... Original
datasheet

154 pages,
3481.71 Kb

NT6TL128T64AR-G1I hynix lpddr2 sdram LPDDR 8Gb LPDDR2 SDRAM hynix NT6TL128M32 Hynix 4Gb LPDDR2 LPDDR2 PoP NT6TL128M32AQ-G1 NT6TL128M32AI hynix lpddr2 /NT6TL256T32AQ NT6TL256T32AS/NT6TL128T64AR NT6TL128M32AI abstract
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Abstract: ) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 5= 220-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) 5 REV 1.0 02/2013 4Gb/8Gb LPDDR2-S4 SDRAM NT6TL128M32AI NT6TL128M32AI(Q , DQ17 DQ19 VSSQ DQ21 DQ23 VSSQ VDDQ DM2 VDD2 VSS LPDDR2 DQ 3 N/C VDD1 4 N/C N/C 5 N/C N/C 6 , DQ28 DQ27 VDDQ DQ24 DQS3_t LPDDR2 CA Power Ground Do Not Use ZQ DQS1_c K DM1 VSS DM0 ... Original
datasheet

153 pages,
3474.31 Kb

NT6TL256T32AQ-G2 ELPIDA mobile dram LPDDR2 LPDDR2 1Gb Memory LPDDR2 216 lpddr2 DQ calibration NT6TL128M32 NT6TL128M32AQ-G0 NT6TL128T64AR-G0 NT6TL256T32AQ-G0 NT6TL128T64AR-G1I NT6TL256T32AQ-G1 elpida lpddr2 hynix lpddr2 NT6TL128M32AI /NT6TL256T32AQ NT6TL128M32AI abstract
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Abstract: , x16) K = 90-Ball BGA (LPSDR, x32) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) Note1: T =Dual Die Package (DDP) Note2: F = Quartic Die Package (QDP , balls through the package LPDDR2 12x12 PoP 1-channel 2x32 package ballout 1 2 3 4 5 6 A B C D E F G H J , Mask: For LPDDR2 devices that do not support the DNV feature, DM is the input mask signal for write ... Original
datasheet

135 pages,
3155.24 Kb

NT6TL64M32AQ ELPIDA LPDDR2 Elpida LPDDR2 Memory Hynix 4Gb LPDDR2 216-ball LPDDR2 1Gb Memory lpddr2 DQ calibration lpddr2 spec HYNIX lpddr2-s2 hynix lpddr2 hynix lpddr2 sdram ELPIDA mobile dram LPDDR2 NT6TL64M32AQ abstract
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Abstract: of the electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock , and external memory. The i.MX50 supports many types of external memory devices, including DDR2, LPDDR2 , Kbyte) · External memory interfaces: - 16/32-bit DDR2-533 DDR2-533, LPDDR2-533, or LPDDR1-400 LPDDR1-400 up to a total of 2 , 168-FBGA 168-FBGA LPDDR2 DRAM memory only. It is not possible to support LPDDR1 or DDR2 on the i.MX50 PoPBGA. · i.MX50 PoPBGA was designed to accommodate a combined LPDDR2 / eMMC PoP memory. The PoP eMMC device uses ... Original
datasheet

137 pages,
1516.2 Kb

VFPv3 emmc emmc 4.4 standard jedec eMMC 4.5 eMMC memory eMMC PoP emmc spec LPDDR1-400 153 ball eMMC memory lpddr2 pcb design emmc Pin assignment eMMC impedance lpddr2 emmc eMMC 4.4 IMX50CEC MCIMX50 IMX50CEC abstract
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Abstract: electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to , i.MX50 supports many types of external memory devices, including DDR2, LPDDR2, LPDDR1, NOR Flash, PSRAM , memory interfaces: - 16/32-bit DDR2-533 DDR2-533, LPDDR2-533, or LPDDR1-400 LPDDR1-400 up to a total of 2 GByte - 8-bit , 168-FBGA 168-FBGA LPDDR2 DRAM memory only. It is not possible to support LPDDR1 or DDR2 on the i.MX50 PoPBGA. · i.MX50 PoPBGA was designed to accommodate a combined LPDDR2 / eMMC PoP memory. The PoP eMMC device uses ... Original
datasheet

134 pages,
1536.55 Kb

MCIMX507CVM8B lpddr2 samsung lpddr2 emmc eMMC 4.41 emmc 4.5 spec eMMC powerdown emmc 4.5 spec samsung 153 ball eMMC memory samsung* lpddr2* pop package eMMC PoP emmc spec Samsung eMMC 4.51 emmc spec samsung IMX50CEC MCIMX50 IMX50CEC abstract
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Abstract: The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of , i.MX50 supports many types of external memory devices, including DDR2, LPDDR2, LPDDR1, NOR Flash, PSRAM , memory interfaces: - 16/32-bit DDR2-533 DDR2-533, LPDDR2-533, or LPDDR1-400 LPDDR1-400 up to a total of 2 GByte - 8-bit , UART2_CTS UART2_RTS Notes on Package Differences · The i.MX50 PoPBGA package supports 168-FBGA 168-FBGA LPDDR2 DRAM , designed to accommodate a combined LPDDR2 / eMMC PoP memory. The PoP eMMC device uses the SD3_DATA[7:0 ... Original
datasheet

135 pages,
1527.9 Kb

VFPv3 eMMC "thermal impedance" eMMC 4.4 eMMC 4.5 emmc 4.5 spec emmc boot sequence emmc controller eMMC data retention eMMC impedance eMMC powerdown Samsung eMMC 4.51 Samsung EMMC "boot mode" SAMSUNG emmc IMX50CEC MCIMX50 IMX50CEC abstract
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Abstract: , including DDR3, low voltage DDR3, LPDDR2, NOR Flash, PSRAM, cellular RAM, and managed NAND, including eMMC , LPDDR2-800 channels - 16/32-bit NOR Flash. - 16/32-bit PSRAM, Cellular RAM (32 bits or less) Each i.MX , /32-bit DDR3-800 DDR3-800 or LPDDR2-800 · Supports up to 2 GByte DDR memory space The On-Chip OTP controller , LPDDR2 DDR3 - Worst case, assuming all SOC I/O operating at 1.8V. NVCC33 NVCC33_IO must always be greater than ... Original
datasheet

105 pages,
881.53 Kb

e-mmc v 4.41 operation mode cortex-a9 c20 manual ARM v7 cortex a9 block diagram ARM TZ API imx 179 lpddr2 layout SONY CMOS sensor imx sony IMX 179 USB HSIC sony IMX cmos Jedec lpddr2 sony imx 175 datasheet abstract
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