500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
ECS-PEC25-1062.5-B-N ECS International Inc PECL Output Clock Oscillator, 106.25MHz Nom, ROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 6 PIN visit Digikey
ECS-PEC25-1250-B-N ECS International Inc PECL Output Clock Oscillator, 125MHz Nom, ROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 6 PIN visit Digikey
ECS-PEC25-1000-B-N ECS International Inc PECL Output Clock Oscillator, 100MHz Nom, ROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 6 PIN visit Digikey
ECS-PEC25-1562.5-B-N ECS International Inc PECL Output Clock Oscillator, 156.25MHz Nom, ROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 6 PIN visit Digikey
ECS-PEC25-1555.2-B-N ECS International Inc PECL Output Clock Oscillator, 155.52MHz Nom, ROHS COMPLIANT, MINIATURE, CERAMIC, SMD, 6 PIN visit Digikey
TRUEINSPECTOR Texas Instruments Atollic TrueINSPECTOR visit Texas Instruments

lpddr2 spec

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Semiconductor, Inc. 1/? Agenda Industry Trends: IT & Mobile LPDDR2 Effect on Battery Life DDR3 , Industry Trends: IT & Mobile LPDDR2 Effect on Battery Life DDR3 Effect on Energy Saving SSD Effect on , LPDDR2 Effect on Battery Life DDR3 Effect on Energy Saving SSD Effect on Efficiency Virtualization , Memory Bandwidth Wide I/O 12.8GB/s 9.6GB/s LPDDR2 2ch. Serial IO 6.4GB/s LPDDR2 3.2GB/s , Multi Screen `13 `14 Green LPDDR2 Introduction · From Low-density MDDR to higher density LPDDR2 Samsung Electronics
Original
lpddr2 lpddr2 datasheet samsung lpddr2 samsung* lpddr2 LPDDR2 1Gb Memory samsung toggle mode NAND 12-DIMM- 640GB HS22V 288GB 192GB 320GB
Abstract: . 13 Simplified LPDDR2 State Diagram . 13 7.1 7.1.1 7.2 Simplified LPDDR2 Bus Interface State Diagram , 7.4.19.3 7.4.20 7.4.20.1 7.4.20.2 7.4.20.3 7.4.21 7.4.21.1 7.4.21.2 7.4.22 7.4.23 LPDDR2 , . 29 LPDDR2: tDQSCKDM Timing . 30 LPDDR2: tDQSCKDS Timing Winbond Electronics
Original
W978H6KB 74164 truth table W978H2KB A01-001
Abstract: . 13 Simplified LPDDR2 State Diagram . 13 7.1 7.1.1 7.2 Simplified LPDDR2 Bus Interface State Diagram , . 31 LPDDR2: tDQSCKDL Timing . 31 LPDDR2: tDQSCKDM Timing . 32 LPDDR2: tDQSCKDS Timing Winbond Electronics
Original
W97AH6KB W97AH2KB
Abstract: . 13 Simplified LPDDR2 State Diagram . 13 7.1 7.1.1 7.2 Simplified LPDDR2 Bus Interface State Diagram , 7.4.19.3 7.4.20 7.4.20.1 7.4.20.2 7.4.20.3 7.4.21 7.4.21.1 7.4.21.2 7.4.22 7.4.23 LPDDR2 , . 29 LPDDR2: tDQSCKDM Timing . 30 LPDDR2: tDQSCKDS Timing Winbond Electronics
Original
W979H6KB W979H2KB
Abstract: , x16) K = 90-Ball BGA (LPSDR, x32) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) Note1: T =Dual Die Package (DDP) Note2: F = Quartic Die Package (QDP , balls through the package LPDDR2 12x12 PoP 1-channel 2x32 package ballout 1 2 3 4 5 6 A B C D E F G H J , according to the command truth table. CA is considered part of the command code. Input Data Mask: For LPDDR2 Nanya Technology
Original
NT6TL64M32AQ hynix lpddr2 ELPIDA mobile dram LPDDR2 Elpida LPDDR2 Memory hynix lpddr2 sdram Hynix 4Gb LPDDR2 lpddr2 DQ calibration 64M32 533MH DDR1066 400MH DDR800
Abstract: Processor Spec Finder at http://ark.intel.com or contact your Intel representative for more information , . 30 2.4.1 LPDDR2 Interface (Pads on Top of Package). 30 2.4.2 LPDDR2 Interface (Pins on Bottom of Package). 31 , 8.3 LPDDR2 Electrical Characteristics , .54 Table. 3-30Supported LPDDR2 DRAM Chips Intel
Original
emmc 4.41 spec finder type 81.11 Manufacturer ID list eMMC Z2760 2002/95/EC
Abstract: , BGA interposers and MSO interposers LPDDR, LPDDR2, LPDDR3 GDDR3, GDDR5 Datasheet DDRA , -4 LPDDR JESD209A LPDDR2 JESD209-2E LPDDR3 JESD209-3 Memory interface analysis in DPOJET , . P7500 Trimode Probeing System with accessories LPDDR2 component package on package interposer 4 , * Highest Accuracy on Faster Slew rates * Slew Rates are about 80% of the Max Spec * DDR3L, DDR4 and , MSO72004 with DPOJET Jitter and Eye Diagram Analysis (Opt. DJA) LPDDR2 BGA and PoP Interposers Tektronix
Original
MSO UPGRADE PACKAGE MSO5000 MSO70000 DSO/MSO5000 DPO7000 DPO/DSA/MSO70000
Abstract: (LPDDR, x16) K = 90-Ball BGA (LPSDR, x32) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 5= 220-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) 5 REV 1.1 04/2013 4Gb/8Gb , DQ20 VDDQ DQ22 DQS2_t VSSQ DQ17 DQ19 VSSQ DQ21 DQ23 VSSQ VDDQ DM2 VDD2 VSS LPDDR2 DQ 3 N/C VDD1 , VDD1 VDDQ DM3 VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3_t LPDDR2 CA Power Ground Do Not Nanya Technology
Original
NT6TL128M32AI NT6TL256T32AQ NT6TL128M32AQ-G1 NT6TL128M32 NT6TL128M32AQ-G0 NT6TL256T32AQ-G1 NT6TL256T32AS/NT6TL128T64AR R0-R13
Abstract: (LPDDR, x16) K = 90-Ball BGA (LPSDR, x32) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 5= 220-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) 5 REV 1.0 02/2013 4Gb/8Gb , DQ20 VDDQ DQ22 DQS2_t VSSQ DQ17 DQ19 VSSQ DQ21 DQ23 VSSQ VDDQ DM2 VDD2 VSS LPDDR2 DQ 3 N/C VDD1 , VDD1 VDDQ DM3 VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3_t LPDDR2 CA Power Ground Do Not Nanya Technology
Original
NT6TL256T32 NT6TL128T64AR-G1I NT6TL128T64AR-G0 NT6TL256 NT6TL256T32AQ-G2 NT6TL256T32AQ-G0
Abstract: DDR2, DDR3, DDR4, LPDDR, LPDDR2, or LPDDR3. The B4622B provides four SW tools in one set covering , , DDR3, or DDR4 and B4623B bus decoder for LPDDR, LPDDR2, or LPDDR3 validation provide complete , , LPDDR2, or LPDDR3 validation provides complete protocol decode of memory transactions using an Agilent , either or both edges of clock (spec) mode (spec) 4 Gb/s on 68 channels per U4154A, clocking on either , U4154A, using either or both edges of clock (spec) mode (spec) 2.8 Gb/s on 68 channels per U4154A Agilent Technologies
Original
B4608A 5990-7513EN
Abstract: IS43/46LD16640A IS43/46LD32320A 1Gb (x16, x32) Mobile LPDDR2 S4 SDRAM PRELIMINARY INFORMATION , DQ24 - DQ31. Input DM0-DM1 (x16) DM0 - DM3 (x32) Input Data Mask: For LPDDR2 devices that do , configured as an 8-Bank memory. This device contains 1,073,741,824 bits (1 Gigabit) All LPDDR2 devices use , , one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the LPDDR2 are burst oriented , to normal operation, the LPDDR2 must be initialized. The following section provides detailed Integrated Silicon Solution
Original
IS43/46LD16640A/32320A IS43LD16640A-25BL IS43LD32320A-25BL IS46LD16640A-3BLA1 IS46LD32320A-3BLA1 IS46LD16640A-25BLA1
Abstract: -Ball BGA (LPDDR, x16) K = 90-Ball BGA (LPSDR, x32) C = 90-Ball BGA (LPDDR, x32) A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 5= 220-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) 5 REV 1.0 03 , VDD2 VSS LPDDR2 DQ 3 N/C VDD1 4 N/C N/C 5 N/C N/C 6 N/C N/C 7 N/C N/C 8 N/C N/C 9 , VSSQ DQ30 DQ29 VSSQ DQ26 DQS3_c VDD1 VDDQ DM3 VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3_t LPDDR2 Nanya Technology
Original
elpida lpddr2 lpddr2 spec HYNIX LPDDR2 SDRAM hynix se 094 HSUL-12 lpddr2 256mb NT6TL16M32AQ/ NT6TL32M16AQ R0-R12
Abstract: IS43/46LD16160A IS43/46LD32800A 256Mb (x16, x32) Mobile LPDDR2 S4 SDRAM ADVANCED INFORMATION , 256Mbit CMOS LPDDR2 DRAM. The device is organized as 4 banks of 4Meg words of 16bits or 2Meg words of , LPDDR2 devices that do not support the DNV feature, DM is the input mask signal for write data. Input , contains 268,435,456 bits (256 Megabit) All LPDDR2 devices use a double data rate archiecture on the , . Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and Integrated Silicon Solution
Original
1066M IS43/46LD16160A/32800A IS43LD16160A-25BL IS43LD32800A-25BL IS46LD16160A-3BLA1 IS46LD32800A-3BLA1
Abstract: IS43/46LD16320A IS43/46LD32160A 512Mb (x16, x32) Mobile LPDDR2 S4 SDRAM ADVANCED INFORMATION , 512Mbit CMOS LPDDR2 DRAM. The device is organized as 4 banks of 8Meg words of 16bits or 4Meg words of , LPDDR2 devices that do not support the DNV feature, DM is the input mask signal for write data. Input , contains 536,870,912 bits (512 Megabit) All LPDDR2 devices use a double data rate archiecture on the , . Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and Integrated Silicon Solution
Original
IS43/46LD16320A/32160A IS43LD16320A-25BL IS43LD32160A-25BL IS46LD16320A-3BLA1 IS46LD32160A-3BLA1 IS46LD16320A-25BLA1
Abstract: for LPDDR2/DDR3 - Up to 400 MHz (ECC supported for 8-bit only and not 16-bit) â'" 8/16-bit NAND , .90 9.5.4.4 LPDDR2 Timing Parameter.70 11.1 Obtaining package dimensions .90 9.5.4.5 LPDDR2 Read Cycle.71 12 9.5.4.6 9.6 DDR3 Timing Parameters .66 LPDDR2 Write Cycle.72 12.1 , : F = current Family: 3 = Standard 5 = Advanced Temp Spec: C = â'"40 to +85C Ta Core: 1 = Freescale Semiconductor
Original
KB/32 KB/16
Abstract: IS43/46LD16640A IS43/46LD32320A 1Gb (x16, x32) Mobile LPDDR2 S4 SDRAM AUGUST 2014 FEATURES , DQ24 - DQ31. Input DM0-DM1 (x16) DM0 - DM3 (x32) Input Data Mask: For LPDDR2 devices that do , . This device contains 1,073,741,824 bits (1 Gigabit) All LPDDR2 devices use a double data rate , /O pins. Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected , LPDDR2 must be initialized. The following section provides detailed information covering device Integrated Silicon Solution
Original
IS46LD32320A-3BPLA1 IS46LD32320A IS46LD16640A-3BLA2 IS46LD32320A-3BLA2
Abstract: C = 3 version A = 79-Ball BGA (LPDDR2, x16) I = 134-Ball BGA (LPDDR2, x32) Q = 168-Ball PoP-VFBGA (LPDDR2) R = 216-Ball PoP-VFBGA (LPDDR2) 3 = 240-Ball PoP-VFBGA (LPDDR2) 5= 220-Ball PoP-VFBGA (LPDDR2) 0 = Wafer (KGD) 5 REV 1.0 03 / 2013 512Mb LPDDR2-S4 SDRAM NT6TL16M32AQ/ NT6TL32M16AQ , B VDD2 DQ15 VSSQ C N/C VDDQ DQ14 D LPDDR2 DQ DQ12 DQ13 E N/C LPDDR2 CA DQ11 VSSQ F N/C N/C Power VDDQ DQ10 G H N/C N/C Ground Nanya Technology
Original
NT6TL32M
Abstract: 1.2Ghz Quad A7 Unknown Unknown Unknown 3384 Android 4.1.1 Tegra 3 1.3Ghz Tegra 3 GPU 1GB LPDDR2 , Android 4.0.3 Tegra 3 1.2Ghz Tegra 3 GPU 1GB LPDDR2 1280*800 3978 10414 2983 3714 314 2464 , 64bit DDR3 64bit DDR3 64bit DDR3 32bit DDR3 LPDDR2 LPDDR2 DDR2 1024*728 1024*728 , determine if core has been implemented correctly to ARM spec. Lower score means possible implementation -
Original
tegra3 arm 9435 nvidia tegra 4 nvidia tegra 3 MPC5645S MPC5606S S12ZVH S12XHY S12HY S12ZVHY
Abstract: DRAM Controller with support for LPDDR2/DDR3 - Up to 400 MHz (ECC supported) â'" 16-bit NAND Flash , .87 9.5.4.4 LPDDR2 Timing Parameter.70 12.1 9.5.4.5 LPDDR2 Read Cycle.71 12.2 Pinout 9.5.4.6 9.6 DDR3 Timing Parameters .66 LPDDR2 Write Cycle , Advanced (A5 only) 6 = Dual Core (A5 & M4) Temp Spec: C = â'"40 to +85C Ta Option: 0N = Standard Freescale Semiconductor
Original
Abstract: with support for LPDDR2/DDR3 - Up to 400 MHz (ECC supported for 8-bit only and not 16-bit) â'" 8/16 , .88 9.5.4.4 LPDDR2 Timing Parameter.71 12 9.5.4.5 LPDDR2 Read Cycle.72 12.1 9.5.4.6 9.6 DDR3 Timing Parameters .67 LPDDR2 Write Cycle.73 12.2 , dissipation spec of ballast IcmaxDC peak Maximum peak DC collector current 0.85 A 1.2A and Freescale Semiconductor
Original
Showing first 20 results.